Table 1 - Main contribution of recent proposals for time-to-digital converters implemented on hardware FPGA Work Parsakordasiabi 2021 [3] Kuang 2018 [13] Zhang 2022 [11] Method PWETM + Tuned TDL (181 ABs @ 250 MHz) + Combinatory Encoder + online calibration RO Luncher + TDL (817 ABs @ 500 MHz) + ones-counter encoder + online calibration PWETM + TDL (165 ABs @ 350 Mhz) + ones counter encoder + online calibration (Embedded ARM) Zhu 2021 [10] DSP TDL (864 Abs @ 600Mhz) + bitscounter + online calibration Main contribution A low-resource ToF TDC is proposed in which linearity is improved through the selection of the best slice output configuration without sacrificing resolution or making additional use of resources. An average precision of 5.76 ps is obtained by multiple measurements of the position of a propagated clock signal on a TDL. A method is proposed to compensate for the influence of voltage and temperature by online calibration based on a ring oscillator. DSP as a TDL component is explored, and a high bin cell utilization rate is achieved by using a 6-bit adder configuration. A bits-counter decoder is used to process the output codes from both the carry-chains and the DSP slice. Cao 2018 [17] TDL (150ABs @ 150Mhz) + Bit realignment + Thermometer encoder + online calibration Garzetti 2021 [16] WUA + Multi-chain TDL (405 @ 150 Mhz) + base-2 logarithm encoder + online calibration Zhang 2021 [18] Ring-oscillator based Vernier-type TDC + programmable TDL (56 Abs @ 500 Mhz) length Jiao 2021 [5] Channel waveform generator (CWG) + TDL (277 Abs @ 400 Mhz) + Transition detector encoder Szplet 2021 [19] Two stages TDC (Vernier + TDL) It is proposed to adjust and realign bins through the manipulation of the LUT function based on time analysis results. This approach achieves a resolution of 18 ps RMS on a Cyclone IV FPGA. TDC comparison between different technological nodes from 65 nm to 20 nm using different configurations of Multichain + WUA architectures Metastable problem between the hit signal and system clock is avoided. The proposed ring-oscillator with programmable frequency makes the TDC design easier and TDC performance less positiondependent. A simultaneous measurement scheme is proposed using a single TDL for two input signals. With this, it is possible to save resources without sacrificing accuracy. A two-stage (VDL + TDL), clock-free TDC is proposed. With this combination of conversion methods is possible to obtain a relatively resolution (13 ps) within a reasonable measuring range (3.4 ns). Song 2020 [20] NUMP TDC + temperature correction High performance within a wide temperature range via real time monitoring and compensation of changes in propagation delays according temperature level. Tang 2021 [21] Multi-Chain Averaging Multichain averaging is developed to improve the TDC linearity. Furthermore, bin realignment, avoidance of clock region crossing and synchronized-enable pulse detector components are considered. (ABs), operational frequency, and postprocessing) and the main contribution for each reported work are highlighted. Table 2 shows the performance information. Most of them focus on improving the results considering a single-channel TDC. The first metric corresponds to the resolution. By September 2023 intuition, it can be assumed that high-end FPGA families can deliver better results. Nevertheless, it can be seen that the improvement is not given by the range of the family but by the design strategy. This behavior is repeated in the case of precision. Note that the abbreviations used in this column are: SSP IEEE Instrumentation & Measurement Magazine 17