Evaluation Engineering - 19

DESIGN FOR TEST

MENTOR TARGETS HIERARCHICAL
DFT AND AUTOMOTIVE SAFETY
By Rick Nelson, Interim Chief Editor
	 Hierarchical DFT methodology and
automotive functional safety have
been two recent areas of focus for Mentor,
a Siemens business. Legacy design-for-test
flows impose inefficiencies when transitioning to a hierarchical methodology,
according to Geir Eide, product marketing
director, Tessent Design-for-Test, at
Mentor. What's required for fast time to
market, he said in a recent phone interview, is optimal end-to-end automation
for hierarchical implementation. And
with respect to automotive functional
safety, the required tools and technologies
extend beyond DFT to embrace a safety
ecosystem that included third-party tools,
added Eide's colleague Lee Harrison, automotive IC test solutions manager at
Mentor.
To address both automation for hierarchical implementation and automotive
functional safety, Mentor in November
introduced two new solutions. First,
the Tessent Connect DFT automation
methodology delivers intent-driven hierarchical test implementation that helps
IC design teams achieve manufacturing
test quality goals faster and with fewer
resources compared with traditional DFT
methods. Second, Mentor also introduced
the Tessent Safety ecosystem, which leverages the automotive IP portfolio of Arm
as part of a Functional Safety Partnership
Program.

the traditional DFT process into smaller,
more manageable elements.
DFT is becoming a critical path to
tape-out, said Eide, adding, "The transition to hierarchical DFT methodologies
is inevitable." Without automation, he explained, engineers need to describe what
they want the tools to do each step of the
way, information from one step must be
carried over to the next, and errors discovered late in the process can result in
time-consuming iterations. With intentdriven automation, engineers can use
fewer, shorter scripts, with the tool handling integration, setup, and pattern generation, resulting in shorter turnaround
time and reliable, sustainable flows.
"Tessent Connect is the optimal way of
implementing the Tessent Shell Flow for
Hierarchical Designs," Eide noted.
Eide said an early adopter of Tessent
Connect is eSilicon, a provider of FinFET
ASICs, market-specific IP platforms, and
advanced 2.5D packaging solutions. By
employing Tessent Connect, he said,
eSilicon improved IC DFT implementation

cost while enabling system-level DFT testing and debug capabilities for a sophisticated next-generation ASIC.
"eSilicon uses Tessent Connect to help
us meet our aggressive production schedules and deliver industry-leading ICs like
those based on eSilicon's neuASIC 7-nm
platform for machine learning," said
Joseph Reynick, director of DFT services
at eSilicon, in a press release. "As design
complexity continues to grow, our system/OEM customers' needs expand from
just focusing on high-quality IC manufacturing test to also providing effective
in-system test and functional debug capabilities. With today's complex 2.5D/3D
devices, we are not shipping in volume
until our chips are fully operational in our
customers' systems, including DFT and
IP test. It would be very difficult to meet
these challenges without the Tessent DFT
portfolio and the efficiencies gained from
Tessent Connect automation."
As part of the Tessent Connect
rollout, Mentor also announced the
Tessent Connect Quickstart program,

Hierarchical DFT
Eide explained that advanced IC designs
can achieve high defect coverage for manufacturing and in-system test by making
use of dedicated on-chip infrastructure
such as embedded compression, built-in
self-test, and IEEE 1687 Tessent Connect
IJTAG networks. But as IC designs grow
in size and integrate more on-chip IP, engineers are increasingly adopting hierarchical DFT approaches that break down

Figure 1: FTTI reduction enabled by Tessent LogicBIST with Observation Scan technology.

JANUARY 2020 EVALUATIONENGINEERING.COM

19
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