Evaluation Engineering - 20

DESIGN FOR TEST

offering detailed flow assessments and customized insights from
Mentor's applications and consulting services engineers to help
IC design teams optimize and automate their DFT processes
when using Tessent Connect.
"The Tessent Connect Quickstart program is the fastest way
to elevate your DFT flow to Tessent Connect," concluded Eide.

Automotive functional safety
Mentor describes its new Tessent Safety Ecosystem as a portfolio
of its automotive IC test solutions with links to its partners, providing an alternative to competing programs based on closed,
monolithic, single-source models.
"New requirements require new test techniques or safety
mechanisms, outside of the scope of traditional DFT," explained
Harrison. "Monitoring and managing all of the different in-system test functions is now critical to the safe operation of an
automotive IC. This often requires a dedicated safety island or
manager." He added that in-system logic test time, with a defined
fault-tolerant time interval (FTTI), is now a critical component
of meeting safety requirements (Figure 1).
"To address the challenge of in-system logic test time," Harrison
said, "Tessent LogicBIST with Observation Scan technology
(LBIST-OST) can reduce the in-system runtime by 10x, enabling
a much reduced FTTI when used in an automotive application."

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EVALUATION ENGINEERING JANUARY 2020

The Tessent Safety Ecosystem includes the following technologies in addition to the new Tessent LBIST-OST:
* Tessent MemoryBIST, which features an automation flow
that provides design rule checking, test planning, integration, and verification at either the RTL or gate level. Because
Tessent MemoryBIST features a hierarchical architecture,
BIST and self-repair capabilities can be added to individual
cores as well as at the top level.
* The Tessent MissionMode product, which provides a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system
to be tested and diagnosed at any point during a vehicle's
functional operation.
* The Tessent DefectSim transistor-level defect simulator
for analog, mixed-signal (AMS) and non-scan digital circuits. Suitable for both high-volume and high-reliability ICs,
Tessent DefectSim measures defect coverage and tolerance.
* Mentor's participation in the Arm Functional Safety
Partnership Program (AFSPP). The Mentor Tessent Safety
ecosystem leverages Arm Safety Ready IP functionalities
like the Cortex-R52 processor, which combines real-time
execution with the integrated functional safety capabilities
of any Arm processor, hypervisor technology to simplify
software integration, and separation functionality to protect safety-critical code.
* Mentor's automotive-grade automatic test pattern generation (ATPG) technology, which detects defects at the transistor and interconnect levels often missed by traditional
test patterns and fault models.
* Close links to Mentor's Austemper SafetyScope and
KaleidoScope products, which add safety analysis, autocorrection, and fault-simulation technology to address
random hardware faults. Austemper technology analyzes
a designer's RTL for faults and vulnerabilities and is capable
of smart fault injection to help safety mechanisms react in
a planned manner for covered faults. Through parallelized
and distributed operation methods, proprietary acceleration algorithms achieve speed-ups of many orders of magnitude over standard gate-level fault injection techniques.
Among the early adopters of key technologies in Mentor's
Tessent Safety ecosystem is Renesas, which evaluated Mentor's
new Tessent LBIST-OST solution in designing one of its newest
automotive processors.
"Leveraging the Observation Scan technology featured in the
new Tessent LBIST-OST solution, we were able to reduce the test
time for in-system Logic BIST by 5x, thereby enabling a much
faster coverage ramp up," said Hideyuki Okabe, director, Digital
Design Technology Department, Shared R&D EDA Division, IoT
and Infrastructure Business Unit at Renesas Electronics Corp.,
in a press release. "This enabled us to reduce our Fault Tolerant
Time Interval...when using Logic BIST as a safety mechanism
and improve the safety response when detecting new defects
in our automotive products. We hope to continue to adopt this
technology going forward for our automotive products."

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