Evaluation Engineering - 24

DESIGN FOR TEST

Figure 4: Implementing DFT at the core group
level is most efficient, avoiding the drawbacks of
both core-level and chip-level DFT.

test time and test pin requirements. DFT
software can help designers configure the
number of input/output test channels to
find the best results.
To reduce area overhead, a single
memory BIST controller can be shared
between multiple memories in multiple
cores. A shared-bus implementation also
allows for better implementation and connection of the bus to the memory BIST
controller. In this flow, the DFT engineer
does not need to alter any functional logic
connected to the memories.
Regarding test power, the designer may
want to add more cores to a group without increasing the test power. Adding an
EDT (embedded deterministic test) lowpower controller can enable better control
of power usage during test.

Perform DFT insertion in RTL
DFT logic has traditionally been inserted at the gate-level design during
or after synthesis. Using this approach
for AI chips comes with two significant
drawbacks.
* It takes about 4 times longer to simulate at gate-level than the RTL, and
about 20 times longer for regression
debug
* If working at the gate-level, any DFT
logic or configuration changes require another synthesis iteration of
the entire design before verification
can be performed
A design may go through many iterations of DFT logic changes before it is

EVALUATION ENGINEERING JULY 2019

finalized. For a huge AI chip, having to
repeat simulation, debug, and synthesis
for each iteration would significantly impact the design schedule.
Insertion of DFT logic in RTL-including IJTAG, memory BIST, boundary scan,
EDT, logic BIST, and on-chip clock controller (OCC)-is faster because changes
can be made without repeating synthesis. RTL-level DFT also allows for early
I/O and floor planning of the chip, which
shortens the whole physical design cycle.
In addition to DFT logic insertion, testability checks can also be done at the RTL
level rather than waiting until ATPG to
find coverage problems. Designers can
achieve higher test quality in less time
by performing DFT checking and fixing
most testability issues at RTL before running ATPG.

Eliminate DFT-to-test iterations
Speaking of eliminating iterations, the
silicon bring-up process can be radically
streamlined. The traditional process of silicon bring-up typically involves the multiple iterations between the DFT domain
and the test/ATE domain for pattern debug, characterization, test optimization,
and test scheduling. The back-and-forth
between the DFT engineer and the test
engineer is particularly inefficient in the
early stages of silicon bring-up when the
dominant source of the issues is still unknown. However, DFT engineers can now
perform the silicon bring-up themselves,
and the test engineers can run diagnosis

in several resolutions from flop-level to
net-level without the help of DFT engineers using a desktop debug solution.
One of the leading AI chip companies,
Graphcore, adopted this solution not only
for silicon bring-up, but also for complete
testing of their parts. They were able to
complete silicon bring-up within three
days, and ship fully tested and validated
parts within the first week, far ahead of
schedule (according to results presented
at the 2018 ITC symposium).

Conclusion
The semiconductor landscape is poised for
the arrival of new ICs specific to the demands of AI applications. As companies
race to get their chips to market, design
teams are adopting DFT techniques that
are better suited to the challenges of AI
chips, including
* Exploiting AI chip regularity
* Performing DFT insertion in RTL
* Eliminating DFT-to-test iterations
These three techniques can result in
significant reductions in time-to-market
for large, complex AI chips.
Rahul Singhal is a Technical
M ar ke tin g E n gine er-
Tessent Solutions, at Mentor,
A Siemens Business. His focus is on the industry requirements in the areas of ATPG, compression,
low pin count testing and DFT for AI chip
architectures.

Evaluation Engineering

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