Evaluation Engineering - 17

1687-based network provides access to
all of the test IP distributed throughout
the design.
The test IP can consist of any IJTAGcompliant test IP. The hierarchical network of SIB (scan insertion bit) switches
allows for versatile and efficient communication to the test IP. An IEEE 1149.1 TAP
(test access port) provides external access
to the IJTAG network and is primarily
used within the manufacturing test environment. At the heart of the architecture
shown in Figure 1 is Mentor's Tessent
MissionMode controller, which can take
over the TAP signals and drive any test
or diagnostic commands to any and all of
the test IP in the IJTAG network.
The Tessent MissionMode controller
can be configured to operate in two different modes: CPU access mode and direct
memory access (DMA) mode.
In CPU access mode, the controller supports parallel read and write operations
to and from a CPU bus. The controller
performs the parallel-to-serial and serialto-parallel data conversion necessary to
transport information between the CPU
bus and the IJTAG network. This mode
supports a module or system-level communication architecture, as illustrated in
Figure 2. A service and/or safety processor can access each Tessent MissionMode
controller through the appropriate interface logic, and hence any on-chip test IP
through any on-chip bus (e.g. APB) or any
vehicle bus such as CAN (controller area
network) or I2C (inter-integrated circuit).
In the DMA mode, the controller reads
command data preloaded in nonvolatile
memory. Multiple test sequences can be
stored and subsequently retrieved in any
order and as many times as desired during system operation.
In addition to accessing the entire
chip IJTAG network through the TAP,
one or more in-system tests can also be
configured to communicate directly to
the component under test. This has the
benefit of reducing communication latency, which can be critical for certain
tests. One important example is nondestructive memory BIST. In this form
of testing, the memory BIST controller
tests the memory using a series of short
sequences of transactions, often referred

to as bursts. A burst will typically only
last for a small number of clock cycles
and target different memory locations
each time. The entire memory is therefore tested over a large number of short
memory BIST sessions. The approach is
nondestructive because the memory locations that are modified by a burst are
saved and restored during each burst by

the memory BIST controller. Functional
performance is not significantly affected
because the bursts are only initiated
when arbitration logic determines the
memory is free. If memories are only to
be tested at power-on, then the more traditional destructive memory BIST test
can be used. In this case, latency is generally not an issue and a single Tessent

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Evaluation Engineering

Table of Contents for the Digital Edition of Evaluation Engineering