AUTOMATED TEST Figure 2: Board/systemlevel test communication architecture. MissionMode controller interfacing to the TAP is sufficient. Logic BIST is another popular form of in-system test that can be accessed through the MissionMode controller. This test solution involves the on-chip generation of random patterns that are applied to scan chains. A recent improvement to this approach is a hybrid test solution that integrates both ATPG compression and logic BIST, as illustrated in Figure 3. Both of these solutions are typically required within automotive devices: ATPG compression for high-quality manufacturing test, and logic BIST for power-on, poweroff, and on-line logic testing. There are clear advantages to combining the two solutions. In particular, area overhead can be reduced as the two solutions use much of the same on-chip DFT Figure 4: Low power logic BIST architecture. Figure 3: Hybrid ATPG compression and logic BIST architecture. 18 EVALUATION ENGINEERING NOVEMBER 2019 resources. For example, they both make use of scan chains and related test clocks. The main difference between the two solutions lies in the on-chip logic feeding test data to the scan chains and processing the test response data coming out of the scan chains. There are also similarities in this logic so that the logic of the two solutions can be effectively combined to support both approaches. An important aspect of applying logic BIST periodically during functional operation is to limit power dissipation in order to minimize any effects on other parts of the system not under test. Reducing power during logic BIST operation can be achieved by minimizing toggle activity during loading and unloading of the