Evaluation Engineering - 19

random patterns and responses. The architecture shown in Figure 4 provides
the ability to reduce scan toggle activity
by periodically replacing random data bits
with constant values. The architecture enables any arbitrary toggle rate to be programmed in the field. Toggle rates can be
decreased while maintaining test coverage
with some increase in pattern count.

Achieving very low DPPB
with defect-oriented test
The widely used methodology for testing
digital circuits is to add scan-test structures to the design and then deliver test
patterns through these structures that
reveal defects when the chip responses
are observed. The approach has been in
use for decades and is based on modeling circuit defects to a level of abstraction that enables a computationally efficient test-pattern generation process.
The simple stuck-at fault model, which
models circuit defects as logic nets stuck
at either a 0 or 1 value, was initially used.
More complex fault models were added
over the years to account for new defect
types that appeared as the industry transitioned to new technology nodes. Among
the more recently adopted fault models
were the transition, bridging, open, and
small-delay faults.
However, with the move to smaller
geometries these fault models and associated test patterns are becoming less
and less effective at ensuring desired
quality levels. The main problem is that
all of these existing fault models only consider faults on cell inputs and outputs and
only some defects on interconnect lines
between these cells. In other words, only
faults abstracted to the netlist level are
explicitly considered.
It was shown in larger technology nodes
(< 90 nm) that more defects occur within
the cell structures. For the more advanced
technology nodes and associated fabrication technologies, some estimates put the
number of defects found within cells to
represent almost half of all circuit defects.
Various types of interconnect defects are
becoming prevalent as well. Thousands of
patterns are typically produced during the
normal ATPG process. As a result, although
traditional fault models do not target

Figure 5: Defectoriented flow for
automotive-grade test
quality.

cell-internal and various cell-external defects explicitly, many
of these defects end
up being detected
by chance. However,
when considering
millions of gates in a
design and the need
for very low DPPB
levels, it is not effective to rely on luck to
detect all potential
defects. The more
advanced Cell-aware
Test (CAT) methodology directly targets
physical defects internal to each cell,
and the layout-aware bridge extraction
methodology targets specific bridge defects on the interconnect between the cells.
Leveraging the proven layout-based
design and library cell together with advanced critical area analysis (CAA) of the
defect locations, the generation of manufacturing test patterns that effectively
target defects at the transistor level inside
cells, between adjacent cells, and in the
interconnect based on critical area can be
achieved. Published manufacturing test
results demonstrate that these pattern
types uniquely detect defects.
This technology is a two-step process
to generate defect-oriented patterns
targeting the automotive-grade quality
requirements, illustrated in Figure 5. The
first step is a characterization process
to create accurate models for both cellinternal and design-related defects based
on layout, design for manufacturability
(DFM) rules, and CAA. The output is a
user-defined fault model (UDFM) that
describes the defects for both pattern
generation and failure diagnosis. The
second step is to create the patterns
based on the generated defect models
(UDFM). The defect coverage improvements may eliminate the need for other
costly procedures such as system-level
test and performance margining.

Analog fault simulation for highquality mixed-signal circuit test
Cell-aware test, layout-aware test, and
other advanced digital test solutions are
going a long way in improving device
quality. It turns out, however, that the
majority of field failures in automotive
devices now occur within the mixedsignal portion of the chip, as shown in
Figure 6. This is not that surprising as
the successful elimination of most digital defects means that any remaining defects will likely be mixed-signal in nature.
These defects, albeit often small in number, cannot be tolerated in safety-critical
Figure 6: Source of electronic breakdowns in
mixed-signal automotive ICs.

Digital 3.6%
Interconnect
17.9%

Analog

78.6%

Source: ON Semiconductor
NOVEMBER 2019 EVALUATIONENGINEERING.COM

http://www.EVALUATIONENGINEERING.COM

Evaluation Engineering

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