Evaluation Engineering - 20

AUTOMATED TEST

automotive applications. Solutions are
therefore needed to address this testing
shortfall.
A basic prerequisite to automating
the generation of analog tests is an automated means of measuring the fault
coverage achieved by any test. Although
fault simulation for digital circuitry has
been commercially available for almost

30 years, analog fault simulation has only
until very recently been discussed in academic papers and conferences. Being first
to market with its commercial solution
for analog fault simulation, Mentor offers
a mature product that continues to be
enhanced with new features.
The basic approach is to measure the
coverage of opens and shorts and related

parametric variations within a transistorlevel netlist. Coverage of a given defect
is determined by evaluating a change in
the circuit response in the presence of the
defect through analog simulation. What
makes this approach now practical is the
use of a number of significant speed-up
techniques to reduce the analog simulation time by several orders of magnitude
over simulating each defect one at a time
on the flat netlist. These techniques include such things as likelihood-weighted
random sampling to ensure most time is
spent simulating the most likely defects,
and mixed-model simulation where the
highest-level model or netlist is used for
each sub-circuit instance that does not
contain the defect being simulated. This
new automation enables a number of analog test-related capabilities. First, existing
analog tests can be evaluated for their effectiveness. Tests that do not cover any
additional defects can be eliminated to
reduce test time and cost. The new defect
coverage metric can also be used to guide
the generation of efficient new tests.

Defect tolerance and
FMEDA analysis
Mentor's analog fault simulator, Tessent
DefectSim, can also be used to measure
a circuit's ability to continue to operate
within acceptable operational parameters
in the presence of various defects. This defect tolerance analysis is very important
in automotive applications as it directly
relates to long-term reliability. In the most
general case, it is assumed that functional
logic is monitored by some safety mechanism such as ECC or BIST. The impact of
a defect can then be classified as shown
in Figure 7.
Defects in the q1 and q2 quadrants do
not affect the correct functional operation
of the circuit and thus do not adversely
affect safety. Defects in the q3 quadrant
do affect functional operation but are detected by the safety monitor, which places
the circuit into a safe state. Defects in the
q4 quadrant also effect functional operation and are unfortunately not detected
by the safety monitor. The q4 defects,
therefore, result in an unsafe state. Defect
tolerance is then calculated as follows:
1 - q4 / (q1+q2+q3+q4).

20

EVALUATION ENGINEERING NOVEMBER 2019
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Evaluation Engineering

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