Evaluation Engineering - 27

necessary to only perform the Modulo-2
sum, or XOR, of the data bits in the binary
stream to obtain the parity bit.
Once the even parity is obtained, the
odd parity can be obtained as the inverse
of the even one.
As stated before, this project implements two variants of the binary parity
generator and checker. Both have an even
output bit and an odd output bit, which
is set to a high level if the corresponding
parity is detected. Also, they have an enable input. If the enable is high, the parity is calculated. Otherwise, both parity
outputs are set to a low level.
In the parallel variant, the generator or
checker obtains the parity bit of a 9-length
binary stream. With this length, it can
be used by the generator as a processor
of 9 bits or as a processor of more than 9
bits by only using the MSB (the 9th bit) as
the cascaded input of another processor.
In Figure 4, the logic diagram of the
9-bit length parallel input parity checker
is shown.

Figure
5: Serial
Input Parity
Generator
Schematic
Diagram

Serial-to-parallel data conversion is
based on Dialog's AN-1120.
When there's no data on the serial input
pin the serial bus is held high. When a
byte is going to be sent, a logic low start
bit is sent before the byte to indicate a
transmission. After that, the eight data
bits are sent and finally, a stop high-level
bit is sent. This sequence can be seen in
Figure 6.
Within several GreenPAK ICs the SPI
block can be used to implement the serialto-parallel conversion. The serial communication must have a 9600 baud rate.
A falling edge detection is implemented
to detect the start bit. When it is detected,
a connection flag bit is set so two coun-

Figure 4: Parity Generator Logic Diagram

Table 1 shows a functional table of the
parity generator and checker.
D0-D8

Enable

Even
Output

Odd
Output

XXXX

Even Input

Odd Input

Table 1: Parity Generator Functional Table

In the serial variant, the input stage
includes a serial to parallel conversion,
so the output of the converter is connected to the parity generator circuit.
This scheme is shown in Figure 5.
This variant also includes an additional cascaded input, so more bits can
be processed by using several 8-bit parity
checkers.

ters/delays are triggered. One of them,
titled Bit Timer, is configured to have
a period equal to the bit time duration
(1/9600). The other counter, titled Frame
delay, is configured to have a delay time
equal to the 10-bit frame period (10/9600).
With these timers, the SPI block is connected so that the serial data input pin is
connected to the MOSI input and the Bit
Timer output is connected to CLK. The
eight data bits are received by the SPI block.
Additional logic is used for controlling
the clock signal, so when the frame period
has elapsed, the SPI clock stops and the
data is held on the register.

More details of the SPI to Parallel
converter can be found in Dialog's
AN-1120.

Implementation and Configuration
As described before, there are two variants of parity generator and checker,
implemented with two different Dialog
GreenPAKs.
The parallel input variant is implemented with SLG46536V.
To implement the bit inversion, as
shown in Figure 4, 9 LUT's were used,
configured as inverters. This can be seen
in Figure 7.
The XOR is implemented to obtain the
resulting bit for each nibble of data by using two 4-bit LUTs. They are configured
as shown in Figure 8. As there aren't
more 2-bit LUTs available, the XOR between the two nibbles is processed with
the 3-bit LUT3 with the third input connected to GND.
To obtain the resulting bits of processing the 9-th bit input, 3-bit LUT11
and 3-bit LUT12 are used by connecting
input 2 to ground. They are configured
as shown in Figure 9 and Figure 10 to
process the XOR and XNOR respectively.
Finally, the even bit and odd bit are
individually AND'ed to the enable bit and
VDD using 3-bit LUT14 and 3-bit LUT15
respectively. These configurations can be
seen in Figure 11 and Figure 12.
The entire parallel input Parity
Generator and checker design is shown
in Figure 13.
The serial input variant is implemented with the SLG46536V. It has two matrixes that can be interconnected, so
one of them was used to implement the
serial to parallel converter and the other
to implement the parity logic.

Figure 6: Serial Data Frame
NOVEMBER/DECEMBER 2020 EVALUATIONENGINEERING.COM

http://www.EVALUATIONENGINEERING.COM

Evaluation Engineering

Table of Contents for the Digital Edition of Evaluation Engineering