Evaluation Engineering - 28

LOGIC ANALYZERS

Figure 7:
Bit Inverter

Figure 8:
XOR Processor

Figure 9:
9-th Bit XOR

In Figure 14 and Figure 15, the Matrix 0 of the
SLG46536V can be seen with the implemented serial to
parallel converter.
Pin 10 is used as the serial data input. As mentioned
before, a falling edge detector with a delayed output is
implemented with P DLY0. This signal is used to indicate
the start of reception, held by DFF0 and DLY6.
Once the transmission has started, CNT2 generates
a signal with a frequency equal to 9600. This is done by
dividing the output clock of the oscillator, which corresponds to the internal ring oscillator controlled by the
2-bit L1. CNT2 configuration can be seen in Figure 16.
The data is received by the SPI block, configured in
S2P mode and with an 8-bit data length. This can be seen
in Figure 17.
The reception is enabled until CNT5 reaches the maximum count, which is configured to be 8/9600 to receive
the eight data bits. The counter uses the internal RC oscillator (2 MHz) divided by 24. Its configuration can be
seen in Figure 18.
Once the data is received, it is processed by the logic implemented in Matrix 1. Matrix 1 can be seen in Figure 19.
Data bits are obtained from the parallel output of the
SPI Module. The XOR of the eight bits is implemented
with 3-bit LUT10, 4-bit LUT1, 2-bit LUT4 and 2-bit LUT5.
Finally, 2-bit LUT6 and 2-bit LUT7 implement the XOR
and XNOR with the cascaded input (Pin 12) respectively.
The enable controls are AND'ed by 3-bit LUT8 and LUT9.

Results
To test the implementation, the two variants of binary
parity generator and checker were analyzed separately.
The parallel input Parity Generator was tested by generating known data to be processed by the Generator so
the output can be checked. In this case, the used data was

28

EVALUATION ENGINEERING NOVEMBER/DECEMBER 2020

Figure 10:
9-th Bit XNOR

Figure 11:
Even Output Control

Figure 12:
Odd Output Control

Figure
13: Parallel
Input Parity
Generator
and Checker

Figure
14: Serial
to Parallel
Converter
(Matrix 0)
Figure
15: Serial
to Parallel
Converter
(Matrix 1)



Evaluation Engineering

Table of Contents for the Digital Edition of Evaluation Engineering

Editor's Note: A Technical Look at the Year that Was
By the Numbers
5G Test: Test industry keeps pace with 5G advances
Portable Instruments: Compact analyzers and scopes serve lab, field, factory, and home
Cybersecurity: Establishing Trust in Cybersecurity for Embedded Systems
Embedded Systems: An 8 GHz PXI Dual SP8T Multiplexer Based on MEMS Swtiches
Logic Analyzers: Binary Parity Generator and Checker
Featured Tech
Tech Focus
Smart Fabrics: Smart Fabrics Go to the Head of the Class
Evaluation Engineering - 1
Evaluation Engineering - 2
Evaluation Engineering - 3
Evaluation Engineering - 4
Evaluation Engineering - 5
Evaluation Engineering - By the Numbers
Evaluation Engineering - 7
Evaluation Engineering - 5G Test: Test industry keeps pace with 5G advances
Evaluation Engineering - 9
Evaluation Engineering - 10
Evaluation Engineering - 11
Evaluation Engineering - 12
Evaluation Engineering - 13
Evaluation Engineering - 14
Evaluation Engineering - 15
Evaluation Engineering - Portable Instruments: Compact analyzers and scopes serve lab, field, factory, and home
Evaluation Engineering - 17
Evaluation Engineering - 18
Evaluation Engineering - 19
Evaluation Engineering - Cybersecurity: Establishing Trust in Cybersecurity for Embedded Systems
Evaluation Engineering - 21
Evaluation Engineering - 22
Evaluation Engineering - 23
Evaluation Engineering - Embedded Systems: An 8 GHz PXI Dual SP8T Multiplexer Based on MEMS Swtiches
Evaluation Engineering - 25
Evaluation Engineering - Logic Analyzers: Binary Parity Generator and Checker
Evaluation Engineering - 27
Evaluation Engineering - 28
Evaluation Engineering - 29
Evaluation Engineering - Featured Tech
Evaluation Engineering - 31
Evaluation Engineering - Tech Focus
Evaluation Engineering - 33
Evaluation Engineering - Smart Fabrics: Smart Fabrics Go to the Head of the Class
Evaluation Engineering - 35
Evaluation Engineering - 36
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