Evaluation Engineering - 29
Figure 21: Serial Input Parity Generator Odd Test
Figure 22: Serial Input Parity Generator Even Test
Figure 17: SPI
Configuration
Figure 16: CNT2
Configuration
In this case, the previous odd data was re-sent so the Odd
output is high, and the Even output is low prior to receiving the
even data. After the even data is received, the Odd detect output
is low and the Even detect output is high.
Figure 18: CNT5
Configuration
Conclusion
We implemented two variants of a binary parity generator and
Checker to be used as an error detection technique for data
transmission. A parity bit is added to the transmitted data to
make the number of 1s either even or odd. This bit is used to
detect errors during the transmission of binary data. Several
commercial IC's can be replaced with Dialog GreenPAKs so that
the application size and cost can be reduced. The two variants
show how the data input method can be either parallel or serial. This is useful for applying the parity generator in different
applications.
Figure 19: Serial Input Parity Checker
X was a bit changing from 0 to 1 periodically. This way, an Odd
result was expected when X is 0 and Even result was expected
when X is 1.
The input signals and the Odd and Even Detect outputs were
measured with a logic analyzer. In Figure 20, the logged signals
are shown to behave correctly.
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Figure 20: Parallel Input Parity Generator Test
The serial input parity generator variant was tested by independently transmitting two bytes, processing them, and verifying
the result. The transmitted bytes were chosen to analyze an odd
byte and an even byte.
In the odd data case, the used data was
In Figure 21, the serial input data and the Odd and Even detect
Outputs, logged with a logic analyzer, are shown.
The odd output is low until the Odd data is received. After that,
the Odd detect output is high and the Even detect output is low.
In the even data case, the used data was 10011001.
In Figure 22, the serial input data and the Odd and Even
detect Outputs, logged with a logic analyzer, are shown.
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Evaluation Engineering
Table of Contents for the Digital Edition of Evaluation Engineering
Editor's Note: A Technical Look at the Year that Was
By the Numbers
5G Test: Test industry keeps pace with 5G advances
Portable Instruments: Compact analyzers and scopes serve lab, field, factory, and home
Cybersecurity: Establishing Trust in Cybersecurity for Embedded Systems
Embedded Systems: An 8 GHz PXI Dual SP8T Multiplexer Based on MEMS Swtiches
Logic Analyzers: Binary Parity Generator and Checker
Featured Tech
Tech Focus
Smart Fabrics: Smart Fabrics Go to the Head of the Class
Evaluation Engineering - 1
Evaluation Engineering - 2
Evaluation Engineering - 3
Evaluation Engineering - 4
Evaluation Engineering - 5
Evaluation Engineering - By the Numbers
Evaluation Engineering - 7
Evaluation Engineering - 5G Test: Test industry keeps pace with 5G advances
Evaluation Engineering - 9
Evaluation Engineering - 10
Evaluation Engineering - 11
Evaluation Engineering - 12
Evaluation Engineering - 13
Evaluation Engineering - 14
Evaluation Engineering - 15
Evaluation Engineering - Portable Instruments: Compact analyzers and scopes serve lab, field, factory, and home
Evaluation Engineering - 17
Evaluation Engineering - 18
Evaluation Engineering - 19
Evaluation Engineering - Cybersecurity: Establishing Trust in Cybersecurity for Embedded Systems
Evaluation Engineering - 21
Evaluation Engineering - 22
Evaluation Engineering - 23
Evaluation Engineering - Embedded Systems: An 8 GHz PXI Dual SP8T Multiplexer Based on MEMS Swtiches
Evaluation Engineering - 25
Evaluation Engineering - Logic Analyzers: Binary Parity Generator and Checker
Evaluation Engineering - 27
Evaluation Engineering - 28
Evaluation Engineering - 29
Evaluation Engineering - Featured Tech
Evaluation Engineering - 31
Evaluation Engineering - Tech Focus
Evaluation Engineering - 33
Evaluation Engineering - Smart Fabrics: Smart Fabrics Go to the Head of the Class
Evaluation Engineering - 35
Evaluation Engineering - 36
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