The File - Sep 1, 2008 - (Page 8)

In Focus | Board-level Test Combine techniques to reduce ICT cost, complexity By Bhaskar Naidu Applications Expert (In-Circuit Test) Agilent Technologies Technological advances are putting tremendous pressures on manufacturing test. Nearly every segment of the electronics industry is affected by the following trends: · Shrinking geometries on increasingly complex PCB assemblies; · Growing usage of sophisticated, high-speed electronic components; · Diminishing access points for in-circuit test (ICT); · High Speed Signal Propagation (HSSP), etc. These are the signs of the times electronics manufacturers have to grapple with, as there are new challenges arising from these developments. The continuous evolution of technology means that innovators of new ICT technology need to stay one step ahead of new waves of test access challenges. For instance, the increasing usage of large ball grid array (BGA) devices and multiple CPUs is pushing up the number of node counts, which need to be addressed at ICT. A traditional way to solve this is to increase the node count capability of the ICT system to match the requirements of the PCB assembly. However, this will also mean an increased test cost for the ICT system, the accompanying fixture cost, as well as higher operational and maintenance cost for the entire solution. It is always a challenge for the test engineer to balance the test cost to maintain competitiveness and to achieve optimised test coverage of the product. In many cases, achieving traditional 100 percent test access is no longer applicable. To get around increasing board density, test engineers are looking into limited-access solutions to Cover-Extend essentially does away with the need for test access. lower their cost of test with new paradigms in ICT. A test technique by Agilent called Cover-Extend technology takes another look at traditional ICT and, using a completely new paradigm, helps manufacturers gain the necessary test coverage even when they are faced with no test access. Cover-Extend is part of the VTEP v2.0 Powered vectorless test suite. It leverages two ICT industry methodologies, Vectorless Test with Enhanced Performance (VTEP) and boundary-scan, to overcome the challenges posed by limited access. Vectorless testing To understand how CoverExtend works, we need to have a broad view of how VTEP functions. The technology has been around since 1993. It is an unpowered test, meaning that the DUT is not powered up during the VTEP test, as opposed to, say, a digital test, where the boards need to be powered so that the ICs are live for the digital test to happen. VTEP is the workhorse of unpowered testing—fast, robust and easy to use. Factors contrib- uting to this include automatic test generation and the auto test debugger. These detect opens on pins of ICs, connectors, sockets, headers—basically, anything that can form capacitive plates. For testing purposes, a lowvoltage sinusoidal signal is delivered as a stimulus through the ICT test probes. All pins are connected to ground except one (and power pins) and the stimulus is applied on the one pin. Signal couples to the VTEP sensor plate as femtofarad capacitance. Electronics board on the sensor plate amplifies the signal and is sent to the ICT for analysis. VTEP can accurately identify the subtle differences between good solder joints and solder opens. The only limitation here is that probe access is required for the pins to be tested. I/O functions of individual pins through the use of only four pins of the test access port: TDI, TDO, TCK and TMS. There is no test access to the nodes in between two boundary-scan devices. But we are still able to cover them through boundary-scan, enabling us to test for open and short faults on the inaccessible nodes. Boundary-scan test The other part of the story for Cover-Extend is boundaryscan. With it’s representation in the IEEE committee, Agilent spearheaded this technology and released it to the industry in the late 1980s with the introduction of the IEEE 1149.1 standard. It has ability to control the Manual debug The use of the boundary-scan cells for testing interconnections is the major application of boundary-scan architecture, searching for opens and shorts plus damage to the periphery of the device. However, with boundary-scan, the debugging process can sometimes be very manual and this technology only works for nodes in between two ICs that have boundary-scan capability. A natural evolution of boundary-scan is the silicon nails test. It takes the IEEE 1149.1 one step further by using boundary-scan chains to automatically test nonboundary-scan devices. With silicon nails, we are testing a non-boundary-scan device that continued on page 0 8 EE Times-India | September 1-15, 2008 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/PCB.HTM?ClickFromNewsletter_080901 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/in circuit test.HTM http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/HSSP.HTM?ClickFromNewsletter_080901 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_080901_EETI02.htm?ClickFromNewsletter_080901

Table of Contents for the Digital Edition of The File - Sep 1, 2008

EETimes India - September 1-15, 2008
Contents
National Semiconductor
Get the Low Down on IEEE 1588 Clock Synchronisation
Tech Insights
DigiKey
Combine Techniques to Reduce ICT Cost, Complexity
Microchip Technology
National Instruments
SME, Educational Programmers Show How NI�Cares
Texas Instruments

The File - Sep 1, 2008