The File - Oct 16, 2008 - (Page 5)

In Focus | Verification Environment eases reconfigurable design, verification By Nachiket Urdhwareshe CEO SoftJin Technologies Pvt Ltd The growing complexity of electronic systems poses major challenges to system designers, especially in terms of the requirements of integrating more functionality in smaller silicon real estate. Speed requirements and power dissipation are likewise emerging as major design issues. All of these must be addressed while keeping tab on the cost of the final product. Moreover, these challenges pull the designer towards different directions when making technology choices for implementing the systems. General purpose processors (GPP) offer the flexibility of implementing different applications and amortizing the costs over different applications, thus keeping the costs low. However, they rate poorly in terms of area, speed and power dissipation. On the other hand, ASICs provide good speed and power characteristics, but as the silicon is personalised to a single application, they lack the flexibility for different applications and can be expensive. Reconfigurable architectures explore the gamut of possibilities between the two contrasting technology choices of GPPs and ASICs. In terms of flexibility, reconfigurable architectures vary based on the binding time of application to the target. There is a range of technologies that can be considered as reconfigurable architectures—from structured ASICs and FPGAs to dynamically reconfigurable architectures. Reconfigurable architectures typically have a regular array of blocks of configurable logic, which is embedded in a sea of programmable interconnects. However, they vary widely in terms of the granularity of the logic blocks. Some are very fine grain architectures suitable for Discuss EDA tools fail ESL design SystemC is still evolving and EDA tools provide system-level support. Do you agree? What do you use for your system-level designs? Discuss… impact on the suitability of platform for an application, its performance and the design methodology to be used. Considering all these concerns, different platforms would exhibit different characteristics, such as depicted in figure 1. No single platform solves all the problems, and the solutions can be as numerous as the problems themselves. Dialling the appropriate settings on these flexible choices of fabrics, implementation approaches and platforms is not a trivial task, and engineers most often fall back on tried and true approaches that have worked for them in the past. Urdhwareshe: A high-level co-simulation environment allows the designer to verify the complete system and perform hardware-software co-design. system. The next task is to explore the optimal system architecture that meets the system functionality with desired performance. When modelling the components of a system, it boils down to three basic components. These are: • Control flow of the design. This is normally described as some kind of instruction set and associated higherlevel languages. The microprocessor in the platform would typically be used to implement this. The processor vendors usually provide various simulation models for verification purpose, as well as tools like compilers, linkers and debuggers for implementation. • Data flow of the design. This is described as a data flow graph that typically has tools for capturing and debugging a data flow graph. Reconfigurable fabric or DSPs might be used to implement this—the former being the preferred choice if performance is a more important concern. Models for such fabric may or may not be available and design teams may have to take care of this. The modelling paradigm employed would vary based on the architecture (a dynamically reconfigurable dataflow continued on page 0 bit processing (FPGAs), while others are coarse grain architectures that target word processing (dynamically reconfigurable processors). Each type has its pros and cons with respect to the application at hand. Naturally, the design methodologies involved also vary depending on the architecture. For implementing electronic systems based on reconfigurable architectures, platforms are created by integrating reconfigurable fabric with other components like microprocessors, DSPs, memories, and peripherals. The coupling of the reconfigurable fabric with the processor (as functional unit, coprocessor, attached processing unit, or stand-alone unit) depends on the granularity and the target application, and has significant Modelling, co-simulation What is required is a systematic approach to breaking the problem down into sub-components and providing the appropriate modelling paradigm for each sub-component, including the control, data and memory paths. In addition, a modelling architecture that uses transaction level semantics and communication channels to model the system design and verification problem is necessary. The main challenge of system-level design is bridging the gap between system specifications and platform implementation to achieve the desired performance and flexibility. To achieve these goals, we need to first build a platform independent simulation model, i.e. a high-level language-based executable specification of the Performance Performance Flexibility Flexibility Technology Technology size size Reuse Power Reuse Power Figure 1: Two different platforms exhibit different characteristics. 5 EE Times-India | October 16-31, 2008 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/FPGA.HTM?ClickFromNewsletter_081016 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200090126_0.HTM?ClickFromNewsletter_081016 http://forum.eetindia.co.in/FORUM_POST_1000039193_1200090126_0.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/ASIC.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/microprocessor.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/DSP.HTM?ClickFromNewsletter_081016 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081016_EETI02.htm?ClickFromNewsletter_081016

Table of Contents for the Digital Edition of The File - Oct 16, 2008

EETimes India - October 16, 2008
Contents
National Semiconductor
Tech Insights
Environment Eases Reconfigurable Design, Verification
Texas Instruments
Digikey
Grasp SystemVerilog Testbench Debug, Analysis
WELCON-2008, ICQMOIT-2008, Power India 2008

The File - Oct 16, 2008