The File - Oct 16, 2008 - (Page 9)

In Focus | Verification Grasp SystemVerilog testbench debug, analysis By Bindesh Patel Technical Marketing Manager Amanda Hsiao Technical Manager SpringSoft, Inc. Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many applications today take advantage of this trend. An important point often missed is the accompanying growth in verification complexity. Indeed, the verification task for a design that is twice as big is actually more than doubled. The verification team has to deal with a bigger state-space and the application, which is what the verification environment attempts to mimic, similarly gets “bigger.” Simply building faster tools like simulators will not solve this problem. Rather, it requires capabilities and associated methodologies that make it easier to set up complex verification environments—environments that in the end ensure that the application on the chip works as expected. SystemVerilog provides a solution that addresses this complexity challenge. It is not simply a new language for describing complex structures, but a platform for enabling advanced methodologies and automation. Each of the three key aspects of SystemVerilog has a significant role. The synthesisable design constructs that have been added to SystemVerilog make it possible for designers to code at a higher level of abstraction, often mapping more accurately to the function they are designing and the way they think about it. The new assertions capability allows users to very concisely describe a behaviour that needs to be checked. But it is the verification aspect that provides the biggest bang for the buck, as evidenced by its rapid adoption. The verification component of SystemVerilog brings high- Figure: Hierarchy representation and class inheritance view critical to testbench code comprehension. level programming capability to design and verification teams. In the past, many teams used a C/C++ testbench, native or SystemC-based, to drive a more efficient, realistic test of the design. SystemVerilog brings structure to this process by providing a standard objectoriented language with which to do the same. Tools can now be developed to support a more standard, structured process in a way that is not intimidating to the engineers who previously coded in Verilog or VHDL and are not familiar with a language such as C++. Enhanced capabilities The SystemVerilog testbench (SVTB) language still resembles Verilog code for the most part. Additionally, it includes built-in support for functionality that is commonly needed during verification, such as constrained randomisation and coverage monitoring. The relatively simple notion of constrained randomisation allows engineers to develop sophisticated test scenarios with very few lines of code. It is also a natural progression for the object-oriented model to spur standard class libraries and related Open Verification Methodology (OVM) and Verification Methodology Manual (VMM) methodologies. Both OVM and VMM enable engineers to create modular, reusable verification environments in which components communicate with each other via standard transac- tion-level modelling interfaces. Constrained randomisation also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and blockto-system reuse. This reuse can be extended to off-the-shelf verification IP components that can be used to verify specific functionality such as bus protocols like USB. Clearly, the object-oriented nature and constrained randomisation capabilities of SystemVerilog provide a significant leap forward in verification technology. However, all this cool stuff also brings new challenges for the tools that support the verification environment, especially those used for debug and analysis. Two of the main challenges are the debug of dynamic behaviour and static comprehension of the source code. Dumping data The first thing that comes to mind when engineers examine or debug the dynamic behaviour of their designs is waveforms. Some debug tools have taken behaviour analysis to a significantly advanced level by allowing engineers to examine dynamic activity within the context of the source code itself and to trace a specific behaviour back in time with the push of a button. This analysis relies on the well-understood notion of easily recording (dumping) value-change data from simulation. The data is usually recorded in a highly optimised, dedicated database, such as SpringSoft’s Fast Signal Database (FSDB). Once the simulation data has been recorded, tools accessing this database can provide specialised views and engines that automate and make more efficient the process of evaluating and debugging design behaviours. When debug tools also have access to the design source code, they can put twoand-two together to automatically trace to the root cause of problem behaviours. This stateof-the-art design debug and analysis is well accepted today and continually evolving. Unfortunately, this process is not applicable to testbenches. To begin with, there is really no concept of waveforms or value-changes in programmatic testbench code. Instead, SystemVerilog testbenches have classes that can be created at any point in time with functions that are called to perform a particular task (such as drive a random transaction into the design). Most of these functions execute in zero-time. Hence the notion of value-changes and representation of these changes using traditional waveforms do not apply, at least not directly. The SystemVerilog verification component is, for all intents and purposes, a software language. Designers and verification engineers alike rely on debug tools to understand how the design and verification environment is set up. Traditional continued on page 0 9 EE Times-India | October 16-31, 2008 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/testbench.HTM?ClickFromNewsletter_081016 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/USB.HTM?ClickFromNewsletter_081016 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_081016_EETI02.htm?ClickFromNewsletter_081016

Table of Contents for the Digital Edition of The File - Oct 16, 2008

EETimes India - October 16, 2008
Contents
National Semiconductor
Tech Insights
Environment Eases Reconfigurable Design, Verification
Texas Instruments
Digikey
Grasp SystemVerilog Testbench Debug, Analysis
WELCON-2008, ICQMOIT-2008, Power India 2008

The File - Oct 16, 2008