The File - Nov 1, 2008 - (Page 1)

India’s fortnightly focus on electronics design November 1-15, 2008 Multi-core SoCs challenge interconnects By Greg Shippen System Architect Networking Systems Division Freescale Semiconductor, Inc. multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus. The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and sub-systems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition? With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memor y controller and I/O interface device. Board-level buses connected the devices. When higher performance was desired, Shippen: The challenge of parallelising existing code will drive convergence of control, data and management functions onto a multi-core SoC. These board- and system-interconnect protocols were propri- etary. Over time, closed protocols gave way to standardised protocols such as Ethernet, PCI Express or RapidIO. Concurrently, IC technology followed Moore’s law and increased both the number and speed of available transistors at a given price. Together these trends dramatically boosted processor performance. Many generations of silicon devices have leveraged this virtuous cycle. Unfortunately, the rate of increase in single-processor performance has levelled off substantially. The most important contributing factor to this decline has been power. Smaller transistors led to faster switching times. Shrinking transistors made them leakier, which lead to increasing static power. And as transistors switch faster, dynamic power increases. This spiralling power increase highlighted several realities driven by the physics of current silicon process technology. First, individual processor performance will be limited by how much power can be supplied and dissipated in a system. Second, transistor budgets will continue to increase but achievable clock rates will not. Moving to multi-core SoCs With still-growing transistor budgets, the industry has moved quickly to devices with multiple processor cores that integrate memory controllers, application accelerators and I/O interfaces to form a multi-core SoC. Multi-core devices promise significantly increased system performance. The rise of SoC devices has reduced the boundaries between continued on page Optimise software for multi-core processors By Kerry Johnson and Robert Craig QNX Software Systems, Inc. Inside Trends 4 Managing threads, communications in multicore partitioning In the past, software developers could rely on faster, more powerful processors to increase the speed of their applications. The industry shift to multi-core pro- cessors has eliminated this “free lunch.” Now, developers who wish to increase performance must create parallel software that can use multiple processor cores simultaneously. Parallelism is an important design consideration for image processing systems, networking control planes, SCADA applications and other compute-intensive embedded applications. A key metric for such applications is system throughput, and the best way to achieve product differentiation is to either perform operations faster or perform more operations at the same time (i.e. in parallel). Operating systems (OSs) that leverage all available CPU cores and visualisation tools that analyse the system-level behaviour of multi-core designs are key to implementing parallelism successfully. In Focus 8 Improve multi-core hypervisor efficiency Events 10 NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On EGovernance Multiprocessing models OSs vary in how they use multiple processor cores. Some OSs support asymmetric multi-processing (AMP), some support symmetric multi-processing (SMP), and some support both. The key difference between these models is simple—SMP supports parallel continued on page Sponsors 2 5 7 National Semiconductor Texas Instruments DigiKey www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/Ethernet.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/PCI%2BExpress.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/RapidIO.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/SoC.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/interconnect.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/operating%2Bsystem.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/image%2Bprocessing.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/image%2Bprocessing.HTM?ClickFromNewsletter_081101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_071001_GS01.htm http://www.eetindia.com/STATIC/REDIRECT/Newsletter_071001_GS01.htm http://www.eetindia.com

Table of Contents for the Digital Edition of The File - Nov 1, 2008

EETimes India - November 1, 2008
Contents
National Semiconductor
Managing Threads, Communications in Multicore Partitioning
Texas Instruments
DigiKey
Improve Multi-core Hypervisor Efficiency
NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On E-Governance

The File - Nov 1, 2008