The File - Nov 1, 2008 - (Page 10)

In Focus | Multicore/multiprocessor design Improve multi-core hypervisor efficiency continued from page 8 Events NECE 2008 Nov. 6-8, 2008 EXPO XXI India, Greater Noida virtualisation technology to its embedded-class chipset implementations. Intel’s VT-d (or Directed I/O) technology recently came to market in desktop chipsets, providing an important addition to the virtualisation acceleration story. AMD and Power Architecture use the term “IOMMU” for the same general capability. Traditionally, hyper visors needed to emulate I/O devices because each guest operating system could not be trusted to have direct access to DMA and other physical resources, which could inadvertently or maliciously affect other guests. The hypervisor would intercept and emulate all guest I/O requests, creating a performance bottleneck. With IOMMU, the guest can be provided direct access to the I/O device (including DMA). The virtualisation hardware will prevent any I/O access (even from the peripheral itself) from accessing memory outside of the virtual machine. Another major improvement coming to virtualisation hardware is what is referred to as “extended page tables.” Traditionally, the hypervisor must intercept every guest attempt to modify system page tables. The hypervisor maintains a “shadow page table” for each guest, and each guest modification is emulated, accomplishing the desired physical memory partitioning. In the future, hardware page tables will be extended, adding another level so that guest physical memory references will be mapped to a true physical location programmed by the hypervisor. Thus, guest page table references will no longer need to be emulated, removing what is arguably the largest remaining performance bottleneck in virtualisation today. tual machines, a small number of hypervisors have been designed to augment an existing operating system environment with virtual machine capability. For example, the Green Hills Padded Cell hypervisor was designed specifically to execute on INTEGRITY. Unlike traditional hypervisors, Padded Cell runs as a user mode application, with a separate instance for each guest environment (see figure). Separation of guest environments is trusted to the secure and safety certified microkernel, which provides bounded and guaranteed services to each guest. In addition, “native” applications can peacefully coexist with the guest environments, enabling developers to host real-time and/or security-critical applications that cannot be trusted to commodity guest operating systems. that require instant-on access and bullet-proof reliability. In the military and intelligence sector, a hybrid-visor can be used to combine computers and networks managing sensitive information at multiple security levels onto a single PC. In this case, native applications are required to secure the shared HMI devices (screen, keyboard, mouse) as well as to provide a trusted cut-and-paste function between the security domains. Network Enabled Capability Exhibition focuses on NEC, IT and communications for defence and security industries. More details here. Nov. 6-8, 2008 Mumbai Power India 2008 Discuss Going all-ARM With an increasing number of vendors adopting the ARM core, the choices of embedded developers are becoming more limited. Do you agree? Hybrid-visors While most hypervisors were created for the sole purpose of hosting one or more vir- The hybrid-visor architecture has many applications (see table) and enables a number of fascinating usage models, many of which provide increased flexibility and reduced size, weight, power, and cost. For example, a telecom system consisting of multiple blades—one running Linux for the control plane and others for the real-time data plane—can be consolidated onto a single computer, running Linux in a virtual machine alongside the native real-time data plane applications. In automotive infotainment, the hybrid-visor can be used to combine a rear-seat office experience (e.g. running Windows with Internet browsing and Office applications) with the traditional front seat real-time “head-unit” radio and navigation functions Multi-core hypervisors Multi-core microprocessors are now standard in PCs and servers. According to recent surveys, single-chip multi-core designs now account for approximately ten per cent of all embedded designs, with this number slowly but steadily increasing. Desktop hypervisors have already started to take advantage of multiple cores, allowing both standard and symmetric multi-processing-enabled guest operating systems to execute on multiple cores simultaneously. Multi-core architectures can improve the usability of hypervisors. For example, on a dual-core system, a separate virtual machine can be bound to each core, enabling a guaranteed quality of service for each guest. In a hybrid-visor system, real-time applications can be assured optimal response time by being bound to a core independent of the core(s) running guest operating environments. The proliferation of multi-core devices is likely to increase the proliferation of hypervisors—a symbiotic growth for two disruptive technologies. The event features exhibits from power plant and equipment, transmission and distribution, nuclear technology, environmental management, IT, instrumentation and automation, and consultancy segments. Get more details. CSF: Electronics & Components Nov. 14-16, 2008 NSE Exhibition Complex, Mumbai The China Sourcing Fair brings China, Hong Kong and Taiwan suppliers of consumer electronics, computers, telecom products, home appliances and electronic components to India. Go to event site. Wind India 2008 Nov. 25-26, 2008 Chennai Trade Centre, Chennai Conference-cum-exhibition on wind power Click here for more information. User2User 2008 India Nov. 26 Taj Residency Hotel, Bangalore The conference features sixteen technical sessions with customer demonstrations of how they use Mentor Graphics products to address design challenges. Go to the event website. National Conference On E-Governance Nov. 27-28, 2008 Dayananda Sagar Institutions, Bangalore Online Vir tualisation specs to allow shared networking Developers must face parallel programming issues Does symmetric multi-processing suit you? The event explores availability of E-features in remote India through information and communication technologies. The conference highlights secure, trustworthy and reliable systems that enable better applications to better governance. Go to event site. 10 EE Times-India | November 1-15, 2008 | www.eetindia.com http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_NECE.htm?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/I%5E%40%5EO.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_PowerIndia.htm?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_CSF.htm?ClickFromNewsletter_081101 http://forum.embeddeddesignindia.co.in/FORUM_POST_1000039251_1200092262_0.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_WindIndia.htm?ClickFromNewsletter_081101 http://forum.embeddeddesignindia.co.in/FORUM_POST_1000039251_1200092262_0.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_user2user.htm?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/TheFile_081101_EGov.htm?ClickFromNewsletter_081101 http://www.eetindia.co.in/ART_8800528619_1800001_NT_01d8314c.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/ART_8800541985_1800001_NT_54a71680.HTM?ClickFromNewsletter_081101 http://www.embeddeddesignindia.co.in/ART_8800498847_2800001_TA_dcf4dc09.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081101_digikey.htm

Table of Contents for the Digital Edition of The File - Nov 1, 2008

EETimes India - November 1, 2008
Contents
National Semiconductor
Managing Threads, Communications in Multicore Partitioning
Texas Instruments
DigiKey
Improve Multi-core Hypervisor Efficiency
NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On E-Governance

The File - Nov 1, 2008

The File - Nov 1, 2008 - Contents (Page 1)
The File - Nov 1, 2008 - National Semiconductor (Page 2)
The File - Nov 1, 2008 - National Semiconductor (Page 3)
The File - Nov 1, 2008 - Managing Threads, Communications in Multicore Partitioning (Page 4)
The File - Nov 1, 2008 - Texas Instruments (Page 5)
The File - Nov 1, 2008 - Texas Instruments (Page 6)
The File - Nov 1, 2008 - DigiKey (Page 7)
The File - Nov 1, 2008 - Improve Multi-core Hypervisor Efficiency (Page 8)
The File - Nov 1, 2008 - Improve Multi-core Hypervisor Efficiency (Page 9)
The File - Nov 1, 2008 - NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On E-Governance (Page 10)
The File - Nov 1, 2008 - NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On E-Governance (Page 11)
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