The File - Nov 1, 2008 - (Page 8)

In Focus | Multicore/multiprocessor design Improve multi-core hypervisor efficiency By David Kleidermacher Chief Technology Officer Green Hills Software, Inc. A growing number of embedded designs are moving to multi-core architectures, while virtualisation technology is also going mainstream. Moving forward, these two disruptive technologies may feed off each other. This article explains some of the history, future hardware trends and emerging usage scenarios of hypervisor technology, then discusses how multi-core architectures improve the usability and efficiency of hypervisors. Figure: Hybrid-visor architecture. Hypervisor history IBM pioneered the concept of a hypervisor that can host multiple “guest” operating systems on a single hardware platform in its mainframes more than thirty years ago. The company used hypervisors to enable legacy versions of its operating systems to continue to execute on new hardware platforms. In addition, IBM software developers used hypervisors as a convenient platform for developing and testing new operating system features. Here is a list of historical uses of hypervisor technology: • Debugging and testing of privileged code/new architectures • Debugging and testing of software prior to hardware • Running distinct and legacy operating systems on the same hardware • Sandboxes for untrusted software • Consolidation—improved utilisation of a single computer • Aggregation—improved utilisation of many computers • Portability—changing hardware while keeping the same OS and applications • Server provisioning—migration, backup, recovery Despite its obvious utility, hyper visor technology was Application Telecom Multi-level secure workstation Electronic flight bag Software defined radio Healthcare Financial Embedded testing SCADA control system Smart munitions Guest(s) Linux for control plane, management Windows, Linux, Solaris for general users Windows for spreadsheet calculations Linux for waveform Windows for general users Windows, Linux, Solaris for general users Windows, Linux for UI management Windows, Linux, Solaris for operator Linux for UI Native Real-time head unit Real-time data plane Trusted drivers, cross-domain solutions Safety-critical transfer of pilot calculations to avionics system Real-time drivers, security-critical components Secure database, authentication, access control Secure database, authentication, access control Real-time I/O for hardware-in-theloop Safety-critical control applications Real-time, safety-critical munitions programming Automotive infotainment Windows for rear-seat office Table: Applications of the hybrid-visor. largely absent from mainstream computing until the turn of the millennium when VMware demonstrated that virtual machines could run with reasonable performance on commodity PC hardware. Since then, a variety of hypervisor technologies have come to market, including Microsoft Virtual PC, open source XEN, Linux KVM, Parallels, and Green Hills’ Padded Cell. Hypervisor technology was made practical on commodity hardware by a combination of intelligent software and, more recently, hardware acceleration added into the leading mainstream computer architectures. In 2005, Intel launched its Virtualisation Technology (VT), which dramatically improved hypervisor execution speed on Intel architecture-based platforms. Intel has continued to add additional performance and security features to aid hypervisors. AMD has followed a similar path. In the PC world, hypervisors are able to implement “full virtualisation” in which the guest operating systems and their applications are able to run unmodified on the virtual machine. In the embedded world, a number of paravirtualisation (modified guest) solutions have been attempted. However, the per formance of embedded microprocessors has precluded full virtualisation. That may be changing. Hardware trends Recently, Power.org announced the addition of virtualisation acceleration features into the Power Architecture embedded profile that may make full virtualisation practical as implementations come to market in the next couple of years. It is probably a good bet that ARM, MIPS and other popular embedded processor cores will eventually follow suit. In addition, Intel is promulgating its continued on page 10 8 EE Times-India | November 1-15, 2008 | www.eetindia.com http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/hypervisor.HTM?ClickFromNewsletter_081101 http://www.Power.org http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/virtualisation.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/virtualisation.HTM?ClickFromNewsletter_081101 http://www.embeddeddesignindia.co.in/SEARCH/SUMMARY/technical-articles/embedded%2Bprocessor.HTM?ClickFromNewsletter_081101 http://www.eetindia.co.in/STATIC/REDIRECT/Newsletter_081101_ti.htm

Table of Contents for the Digital Edition of The File - Nov 1, 2008

EETimes India - November 1, 2008
Contents
National Semiconductor
Managing Threads, Communications in Multicore Partitioning
Texas Instruments
DigiKey
Improve Multi-core Hypervisor Efficiency
NECE 2008, Power India 2008, CSF: Electronics & Components, Wind India 2008, User2User 2008 India, National Conference On E-Governance

The File - Nov 1, 2008