The File - Jan 1, 2009 - (Page 2)

Trends Chip-package co-design lowers design cost Anand Anandkumar VP Globalization, Sales and Founding Managing Director Magma Design Automation India It is typical that almost all large system-on-chip (SoC) designs are focused on minimising the cost for designing and manufacturing the silicon. The truth, however, is that packaging cost is an equally significant part of the overall cost and manufacturability and controlling cost. Herein lies the value of chip-package co-design. Through co-design it is possible, for instance, to package very complex ICs in low-cost plastic ball grid arrays (PBGAs). With process nodes and die sizes shrinking, the number of consumer products incorporating ICs with flip-chip packaging grows. Unfortunately, flip-chip package manufacturing rules “An integrated chip-package codesign system is designed to handle the package and chip constraints simultaneously.” effort involved in producing the chip. Complex parts with high-speed signals put more constraints on the design of both IC and package, and careful design is required to achieve performance while maintaining have not kept pace with shrinking process technology. As a result, a more precise and efficient method of designing the I/O interface is needed, especially for flip-chip designs. This integrated chip-package co-design method should allow an early feasibility study and have the power to optimise the package and chip interface design while satisfying the tight constraints imposed by both. An effective chip-package co-design solution needs to have quick prototyping capabilities because packaging decisions need to be made early in the design cycle, when the design netlist and/or physical libraries are not yet available. Accuracy in predicting the final implementation is also essential. Otherwise, the design decisions made at the prototyping or planning stage can lead to implementation difficulties that would significantly delay tape-out. On the other hand, a conservative plan may result to the addition of unforeseen costs. A co-design system needs to allow the user to explore multiple scenarios available and to test alternative packaging solutions. With such capabilities, the user can build pro- Do more on EE Times India Ask the author Read related articles • Boost productivity with ESL techniques • Advanced packagestacking fits more functions • Standard sets Pb, Pb-free moisture sensitivity criteria totype designs in various substrate stack-ups and perform feasibility checks to find the cheapest packaging solution. Co-design advantages One of the most important advantages of an integrated chippackage co-design planning environment is its ability to take into account the constraints from both the package and chip sides. When there are conflicts in such constraints, the tool continued on page Find Datasheets Online Looking for parts to specify for your design project? Browse through thousands of datasheets organised by category, by manufacturer, and alphabetically. Search using keywords or part number to quickly access datasheets. Part No. NUP4103FCT1G EVAL-ADF70XX Description Quad TVS array in 5-bump flip chip packaging Development platform for ADF702X family of ISM band transceivers 5V RS232 transceiver with 3V logic interface and one receiver active in shutdown 9-bit parity generator/checker with bus driver parity I/O ports (Rev. B) Quad 2:1 multiplexer/demultiplexer bus switch 65MSPS digital receive signal processor Fixed-point digital signal processor (Rev. N) Dual slot hot swap controller for PCI Express PCI local bus power supervisor 10-bit micro power DAC with an I2C-compatible interface Manufacturer ON Semiconductor Analog Devices LT1330 Linear Technology 74ACT11286 Texas Instruments 74FST3257DR2 AD6620 TMS320C6203B LTC4242 ON Semiconductor Analog Devices Texas Instruments Linear Technology National Semiconductor National Semiconductor Download now… LMC6953 DAC101C081 EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/SEARCH/ART/co%7E%40%7Edesign.HTM http://www.eetindia.co.in/ART_8800475729_1800000_TA_371cf858.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800475729_1800000_TA_371cf858.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800456767_1800000_TA_a8650b19.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/prototyping.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800456767_1800000_TA_a8650b19.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800542044_1800007_TA_60c5794f.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800542044_1800007_TA_60c5794f.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/packaging.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/flip~%40~chip.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/I%5E%40%5EO.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/NUP4103FCT1G-1000038501.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/EVAL-ADF70XX-1000041070.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/LT1330-1000041853.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/74ACT11286-1000043654.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/74FST3257DR2-1000027642.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/AD6620-1000039426.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/TMS320C6203B-1000048408.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/LTC4242-1000043433.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/INDEX.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/LMC6953-1000026200.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/DATASHEET/DETAIL/DAC101C081-1000025198.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101

Table of Contents for the Digital Edition of The File - Jan 1, 2009

EETimes India - January 1, 2009
Contents
Chip-Package Co-Design Lowers Design Cost
National Semiconductor
Sub-100nm Tech Brings EDA Opportunities
Algorithmic Synthesis Enhances Design Efficiency
ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

The File - Jan 1, 2009