The File - Jan 1, 2009 - (Page 6)

In Focus | System -level design Sub-100nm tech brings EDA opportunities By Bikram Garg Manager R&D Mentor Graphics Prior to sub-100nm technology there was a clear demarcation of work between designers and the manufacturing community. The designer community was targeting for better design performance, more design functionality for the same chip area and the manufacturing community was ensuring that the design intent was met with no manufacturing defect. The design rules acted as a policeman ensuring the layout passed to manufacturer meets the constraints (design rules) for sufficient product yield. The basic design rules were constraints on the minimum width of a pattern and the minimum spacing among the patterns required for correct fabrication. This way the designer was isolated about the processes used by the manufacturer to fabricate the chip. However, as the chip manufacturing is moving towards deep sub-100nm technology such as 65nm, 45nm, 32nm the need to have more hand shaking between the two communities has become imperative to achieve higher yield. The yield has decreased considerably at these scales which might delay the adoption of smaller dimensions. The feature scaling is outpacing the manufacturing process changes. Some of the manufacturing processes are hitting a ceiling and the most critical one is lithography. This opens new opportunities for the EDA vendors to come with new tools and design methodology to help adopt smaller dimensions. raphy system with on-axis illumination can be approximated as: Rmin = 0.5 λ/NA under coherent light Where λ is an illumination wavelength, NA is a numerical aperture and Rmin is the minimum feature size. And the lithography pcocess resolution provided is: R = k λ/NA Where k is the Rayleigh criterion which has touched to 0.35 in spite of continuous decrease of wavelength (193 nm) and increase in numerical aperture (NA), showing that the feature technology is decreasing faster than the lithography changes. Some of the new lithography technologies to decrease wavelength are not mature to be made part of the manufacturing process. There are experiments going on Do more on EE Times India Post comment Ask the author Share article Read related articles • Design-manufacturing synergy will win yields in the nm era • Signoff for manufacturability • Exploring FPGA selection and system design architecture Challenges Lithography—The optical resolution limit of a conventional lithog- to increase the NA of the lithography process. The immersion of lens in liquid to increase refractive index thus NA has process issues. Also by increasing numerical aperture (NA) to decrease resolution we are deteriorating the Depth of focus (DOF) which is inversely proportional to NA square. As the Rayleigh criterion has hit below .5 there are various resolution enhancement techniques (RET) devised to achieve same patterns on wafer as on the layout i.e. “what you see is what you get”. They are optical proximity correction (OPC), which modifies the patterns on the mask considering the lithography, Chemical Mechanical Process (CMP) effect so that the effect of below .5 Rayleigh resolution is nullified, Alternate Phase Mask shift (AltPSM) which passes lights through two source path shifted by ½ λ to have destructive interference resulting in doubling the resolution limit and many others like double patterning, AttPSM, etc. Adding these RETs brings in many new complex design rules and also conflicting rules which are not easy for the designers to understand as this requires a learning curve in technology and also the rules are complex. Thus bringing in strong RET in the processes is a solution but can result in more systematic defects in the chip affecting the yield and continued on page 0 Figure: The complete design flow for enhancing designers’ productivity. 6 EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.eetindia.co.in/ART_8800555777_1800000_TA_e770bbe3.HTM?ClickFromNewsletter_090101#cnt http://www.eetindia.co.in/article/sendInquiry.do?articleId=8800555777&catId=1800000?ClickFromNewsletter_090101 http://www.eetindia.co.in/article/emailToFriend.do?articleId=8800555777&catId=1800000?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800516641_1800000_TA_87e77a14.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800553889_1800000_TA_f6a6ab3e.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800538093_1800000_TA_7afb4fa0.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/industry-news/RELEVANCE/Lithography.HTM?ClickFromNewsletter_090101 http://www.eetindia.com/STATIC/REDIRECT/Newsletter_090101_EETI02.htm?ClickFromNewsletter_090101

Table of Contents for the Digital Edition of The File - Jan 1, 2009

EETimes India - January 1, 2009
Contents
Chip-Package Co-Design Lowers Design Cost
National Semiconductor
Sub-100nm Tech Brings EDA Opportunities
Algorithmic Synthesis Enhances Design Efficiency
ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

The File - Jan 1, 2009