The File - Jan 1, 2009 - (Page 7)

In Focus | System -level design Algorithmic synthesis boosts efficiency By Vinod Kathrail Synfora Inc. Designers of consumer product ICs are faced today with the challenges of rapidly increasing complexity, a market with high expectations, and static price points. To stay competitive, design teams must find a way to reduce the cost and improve the efficiency of IC design. This dilemma has gone beyond the capacity of existing methodologies, and the industry is in urgent need of a new approach. Most agree that the solution to improving cost and efficiency is to move to a higher level of abstraction—but what is the best route to get there? Algorithmic synthesis (AS) moves the creation of application engines, or algorithms on silicon, to a higher level of abstraction, giving significant time and cost savings. Deploying AS for this defining part of the IC not only pays immediate benefits, but can also be the critical first step in moving the complete design process to a higher level of abstraction. Once AS is established, the methodology can be used to drive verification and validation upwards too, followed by the hardware/software hand off. Using a step-by-step approach, AS can capture the whole of the IC design, at a level of abstraction capable of quickly handling growth in complexity. highest level, four discrete types of IP: • Application engines (video codecs, wireless modems) • Star IPs (CSU, DSP) • Connectivity and Control IP (USB, DMA) • Memory The application engine (algorithms in silicon) is the most critical and time-consuming part of any IC design: critical because it defines and differentiates the end product; time-consuming because the algorithms are complex, the requirements exacting in terms of power, performance and area, and the algorithm changes significantly with each revision. Complex application engines such as those used in multimedia, imaging, wireless, security and networking domains, are traditionally designed block-by-block, either by reusing previously designed blocks, or by creating new RTL blocks manually. The immense amount of time this latter step takes can force designers to re-use blocks and IP which are not specifically targeted at the current application in order to meet budgets and deadlines, resulting in less than optimal performance. AS methodology AS enables designers to create application engines directly from sequential, untimed C algorithms. To deploy AS, the designer provides a C description of the algorithm, along with a C testbench and design constraints such as clock frequency and throughput. AS then automatically generates synthesisable RTL to fit these constraints. For algorithmically complex designs like application engines, AS results far exceed manual design results in terms of time and cost, without compromising performance. Key features of AS • Architectural exploration for optimal design: Less time spent designing blocks means more time for architectural exploration. With AS, designers can evaluate alternative implementations, each of which can be modified and re-verified as often as necessary, just by changing the specified constraints. This enables them to find the design that yields optimal power, area and performance results. • A complete verification and validation environment: It supports both RTL level verification and system-level validation using SystemC transaction level models. • A single language from architecture to implementation:AS supports hardware synthesis from sequential languages to timed RTL. This means that the same language can now be used for hardware, software and system modelling. • Possible re-use of IP: Can be targeted against specific design criteria. • The building up of a library of algorithms: These can be rapidly modified and deployed to meet new or changed performance targets in successive designs. • Smooth integration: The hardware generated is compatible with existing RTL and SystemC flows for rapid, uniform integration into ICs. Benefits of using AS • Best performance: Extensive architectural exploration results in best performance, without major effort or expense. Do more on EE Times India Ask the author Read related articles • Back to the basics: The art of algorithm implementation • C-Language for FPGA acceleration of embedded software • Automated video algorithm implementation • • • • • Reduced Design Time: AS requires less time for development and enables extensive IP reuse. Reduced area and power consumption: AS has been proven to reduce power/area by 10% or more. Reduced Verification and Integration Time: By using previously verified blocks and creating test benches to validate the RTL, AS significantly reduces time spent on this part of the flow. Flexibility: The advanced exploration capabilities also allow designers to react rapidly to changes in specification. Low risk implementation: AS can be proven on a small project initially, and then gradually extended to larger, more mainstream designs. A typical IC A complex IC for most consumer applications comprises, at the Moving to complete AS usage flow Once AS has been established at the application engine level and these kind of results have been achieved, you can set up an AS usage flow. After the scope and timeline for the initial project have been agreed, there are four stages that you need to follow to make this work successfully: 1. Create the architectural template that captures the required properties of the hardware. The traditional division between architecture and implementation means that the architectural design is based on simulation results and mathematical estimates, which are often not applicable continued on page 0 Figure: Colour conversion and Sobel Edge Detector. 7 EE Times-India | January 1-15, 2009 | www.eetindia.com http://www.embeddeddesignindia.co.in/article/sendInquiry.do?articleId=8800556237&catId=2800004?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/ICs.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800535779_1800000_TA_d1b828ae.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800535805_1800000_TA_224544a8.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/ART_8800535820_1800000_TA_8a94650d.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/algorithms.HTM?ClickFromNewsletter_090101 http://www.eetindia.co.in/SEARCH/SUMMARY/technical-articles/verification.HTM?ClickFromNewsletter_090101

Table of Contents for the Digital Edition of The File - Jan 1, 2009

EETimes India - January 1, 2009
Contents
Chip-Package Co-Design Lowers Design Cost
National Semiconductor
Sub-100nm Tech Brings EDA Opportunities
Algorithmic Synthesis Enhances Design Efficiency
ICETIC 2009, IMTEX/Tooltech 2009, ISA Vision Summit 2009, COMPONEX�NEPCON 2009, Convergence India 2009

The File - Jan 1, 2009