IEEE - Aerospace and Electronic Systems - April 2022 - 31

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device. If using two such devices, it might be possible
to receive 32 MHz or more bandwidth from four channels
provided that both devices were synchronized
together to obtain coherent sampling, and the host PC
can support two USB 3.0 ports operating simultaneously
in SuperSpeed mode [6] with enough data
throughput.
Zynq UltraScaleþ RFSoC [8] is a family of SoC
devices provided by Xilinx that integrate multi-Gigasample
RF data converters (ADCs) into an SoC architecture.
There are three generations of Zynq RFSoC
devices that contain 8 or 16 ADCs with different performance
levels (up to 162.5 GSPS ADCs). The RFSoC
device includes additionally an ARM Cortex-A53 processing
subsystem and programmable logic (FPGA,
UltraScaleþ grade) so that any device of this family
can be considered as a powerful, single-chip, adaptable
radio platform. The connection with a host can be
established by using high-speed connectivity options,
like multigigabit SerDes transceivers, 100 Gb Ethernet,
or PCI Express Gen4. The Zynq UltraScaleþ RFSoC
ZCU216 ES1 Evaluation Kit [9] is the platform for
both rapid prototyping and high-performance RF application
development. It supports direct RF sampling of
sub-6 GHz bands, utilizing high-speed 14-bit RF-ADCs.
Signal acquisition can be performed in multiple channels
operating synchronously since all the ADCs in the
device can share a common clock signal.
The Zynq UltraScaleþ RFSoC platform (see
Figure 3) can provide the acquisition of up to 8 or 16 signals
(depending on the chip version) with a bandwidth of
312 MHz or more thanks to the incorporation of numerous
high-performance ADCs (8 or 16 converters) in a
single chip. Such a system could support all the frequency
bands of interest (e.g., DAB, DVB-T, LTE, 5G).
However, in order to realize a complete RF signal acquisition
subsystem, suitable for signal levels specific for
UHF or VHF receiving antennas, the analog frontend has
to be completely custom-designed, including the balun
circuits, RF filters, and also high-gain low noise amplifiers
(LNAs), since ADC inputs of RFSoC require a relatively
high level of input signals (1 Vpp). Moreover, a
high- performance connection of the RFSoC platform to
the host machine becomes a challenge that involves the
development of different modules of software (like ARM
system/embedded Linux, FPGA logic, PCIe driver, host
application) and may require the purchasing of commercial
intellectual property (IP) blocks. Another solution
may be based on the GBE connection provided by
embedded Linux ARM subsystem or may employ the
FADE library [13] ported to this particular FPGA
Figure 1.
ADC-SoC board with two ADCs (source: https://www.terasic.
com.tw).
APRIL 2022
Figure 2.
BladeRF 2.0 micro board (source: https://www.nuand.com/
bladerf).
IEEE A&E SYSTEMS MAGAZINE
31

https://www.terasic.com.tw https://www.nuand.com/bladerf https://www.terasic.com.tw https://www.nuand.com/bladerf

IEEE - Aerospace and Electronic Systems - April 2022

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