Aerospace and Electronic Systems - August 2018 - 24

Feature Article:

DOI. No. 10.1109/MAES.2018.170149

A Cryogenic 0.35 m CMOS Technology BSIM3.3
Model for Space Instrumentation: Application to a
Bandgap Design
Laurent Varizat, Gerard Sou, Pierre and Marie Curie University
Malik Mansour, Dominique Alison, CNRS, Ecole Polytechnique

INTRODUCTION
Space instrumentation has to face harsh environmental conditions
[1]. These conditions strongly impact the design of scientific instruments as well as electronic circuits. It is particularly important
regarding front-end electronics, which have to be integrated very
closely to the instruments to ensure high performances.
In this case, both sensor and electronics have to face the same
thermal and radiative environment, damaging electronics and reducing their lifetime. In those conditions the design of efficient and
reliable front-end electronics is a challenging trade-off between
performance and reliability. Complementary metal-oxide-semiconductor (CMOS) 0.35 μm technology is widely used in space instrumentation in the frame of Application Specific Integrated Circuits design. It presents a good Total Ionizing Dose (TID) radiation
tolerance and offers quite good performance for many analog and
digital applications. Furthermore, the reliability of this technology
is a real asset for space instruments due to a strong heritage. As a
consequence, CMOS 0.35 μm technology remains a good candidate for the purpose of future space electronics design.
In this article, we introduce the study of a commercial 0.35
μm/3.3 V CMOS technology down to liquid nitrogen temperature.
We present a Berkeley Short-channel IGFET Model (BSIM)3.3
parameters model extraction results used to design a reference
voltage circuit for space instrumentation.

FRONT-END ELECTRONICS FOR SPACE INSTRUMENTATION
In the framework of the future European Space Agency (ESA)
JUpiter ICy moons Explorer (JUICE) mission, a radiation-hard
Authors' current addresses: L. Varizat, G. Sou, Electrical and
Electromagnetism Laboratory, Pierre and Marie Curie University, 4 Place Jussieu, 75252 Paris Cedex 05, France, Email:
(laurent.varizat@upmc.fr); M. Mansour, D. Alison, Laboratory
of Plasma Physics CNRS, Ecole Polytechnique, UPMC Univ.
Paris 06, Univ. Paris Sud, Observatoire de Paris Ecole Polytechnique, 91128 Palaiseau Cedex, France.
Manuscript received July 25, 2017, revised January 17, 2018,
and ready for publication January 29, 2018.
Review handled by P. Daponte.
0885/8985/18/$26.00 © 2018 IEEE
24

CMOS 0.35 μm front-end electronics will be design as a part of the
Search Coil Magnetometer (SCM ) instrument [2].1
The instrument is meant to measure electromagnetic components
of plasma waves emitted around Jupiter and its Ganymede moon. To
achieve the required high magnetic field resolution and to prevent
electromagnetic compatibility perturbations, the magnetic antenna
and its front-end electronics will be accommodated on a boom outside the spacecraft. Because of this specific accommodation, the
electronics will work over a temperature ranging from 150 K down
to 100 K and will have to withstand a TID level of 500 Krads.
A temperature-independent voltage reference circuit is a key
feature to ensure the readout electronics accuracy, but the design
of such feature requires cryogenic design models which are out of
the scope of the foundry model only valid from 230 K to 430 K.

THERMAL STUDY
In some applications, working at cryogenic temperature allows
improving transistor's performances. Nevertheless, an accurate
knowledge of the transistors behaviour at such temperature is
needed to design high performances integrated circuits (ICs). In
[3], authors present an evaluation of AMS 0.35 μm for use in space
application but the temperature range of the study only goes down
to 165 K. The knowledge of transistors behaviour below 165 K is
required for many space applications. Here, we present a study of
CMOS behaviour from 77 K to 300 K.

MATERIAL AND METHODS
A test bench using liquid nitrogen was design to characterise both
n-channel metal-oxide semiconductor (NMOS) and p-type metaloxide-semiconductor (PMOS) transistors of different sizes from
room temperature down to 77 K [4]. Sizes are chosen in order to
cover the typical transistors dimensions implemented in low noise
electronics: 50 μm × 0.35 μm, 50 μm × 10 μm and 1,000 μm × 10
μm. Figure 1 shows the layout of a typical NMOS transistor. The
IC test sample is placed in a cryostat which immersion depth is
controlled by a microcontroller to stabilize the temperature at a
given level.
1

JUICE website: http://sci.esa.int/juice/.

IEEE A&E SYSTEMS MAGAZINE

AUGUST 2018

http://sci.esa.int/juice/

Aerospace and Electronic Systems - August 2018

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