Aerospace and Electronic Systems - August 2018 - 25
Several BSIM3.3 models were extracted to cover several temperature ranges from 77 K to 300 K using IC-CAPTM software. We
implemented them to generate a library for electronic design automation (EDA) tools, like CadenceTM, allowing low temperature
integrated circuits design.2
CURRENT-VOLTAGE MEASUREMENTS
The foundry model under study is meant to work from 230 K to
430 K. Figure 2 shows a foundry model simulation result, measurements, and extracted model transistor of the drain current temperature dependency for a given size and bias point. Below 230
K, a nonagreement between measurement and simulation growing
as the temperature decreases is observed. At low temperature, the
foundry model accuracy is not enough to design high performances ICs because they don't implement low temperature effects on
doped silicon conduction. These effects are presented later in the
section called Thermal Study.
In order to fit the measurements, NMOS and PMOS extracted
models are split into three submodels. A first one covers the thermal range [77 K; 150 K], a second one cover the range [150 K;
250 K], and the last one corresponds to the foundry model [250
K; 430 K].
One of the most important temperature dependent parameter is
the threshold voltage Vth0 which defines the gate bias voltage needed to create a conducting path between drain and source terminals.
Table 1 shows the threshold voltage variation with respect to temperature. The absolute value of the threshold increases as the temperature decreases implying the need of a higher bias voltage when
working at low temperature. For PMOS transistors, a drift of half a
volt is observed from room temperature down to 77 K and reaches
the value of −1.2V. These results with the results presented in [5].
Furthermore, the temperature modifies the silicon conductance. Figure 3 shows the output conductance, gds, which quantifies the drain current variation in function of a drain-source voltage
variation while keeping the gate-source voltage constant (1):
g ds =
2
∂I D
∂VDS
A standard NMOS 50μm × 10μm transistor's layout.
Figure 2.
PMOS extracted model simulation on a wide temperature range compared to foundry model and measurements. Size of the transistor is 50
μm × 10 μm with {VGS;VBS;VDS} = {3.3 V; 0 V; 3.3 V}.
Table 1.
V th0 Temperature Dependency for 0.35 μ m NMOS and
PMOS Transistors
300 K
200 K
150 K
100 K
77 K
NMOS
0.5 V
0.58 V
0.66 V
0.72 V
0.76 V
PMOS
−0.7 V
(1)
VGS
This library is available on request with respect to foundries
policies.
AUGUST 2018
Figure 1.
IEEE A&E SYSTEMS MAGAZINE
−0.9 V
−1.0 V
−1.2 V
−1.2 V
25
Aerospace and Electronic Systems - August 2018
Table of Contents for the Digital Edition of Aerospace and Electronic Systems - August 2018
Contents
Aerospace and Electronic Systems - August 2018 - Cover1
Aerospace and Electronic Systems - August 2018 - Cover2
Aerospace and Electronic Systems - August 2018 - Contents
Aerospace and Electronic Systems - August 2018 - 2
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