Aerospace and Electronic Systems - August 2018 - 26

Cryogenic 0.35 μ m CMOS Technology

Figure 3.

GDS output conductance when sweeping VDS from 0 V to 3.3 V and for
VGS = 1.2 V, 1.8 V, 2.4 V, 3.0 V, respectively. Each measurement is performed at 100 K, 150 K, and 200 K, respectively. Arrows represents the
temperature trends for each VGS. Measurements (dots) and simulation
results (lines) are obtained for a 50 μm × 10 μm NMOS transistor.

Figure 4.

CG-DSB temperature dependency for VG-DSB sweep for a 50 μm × 10 μm
PMOS transistor at 100 K, 150 K, and 200 K.

We observe the conductance evolves conversely with the temperature, as expected. We also observe a good agreement between
measurements and extracted model simulations curves when
sweeping VDS and VGS at 100 K, 150 K, and 200 K respectively.

CAPACITIVE MEASUREMENTS
Capacitive measurements are useful to extract physical parameters
of BSIM3.3 model. Figure 4 shows the capacity between the gate
and the drain-source-bulk in function of its bias voltage. No significant differences in capacitive measurement from 300 K down
to 77 K are observed except a slight offset attributed to Vth drift.

DOPED SILICON CONDUCTION PROPERTY AT LOW
TEMPERATURE
Transistors temperature-dependent behaviour is mainly due to
two physical phenomena: the charge carrier variations as well
as the charge carrier mobility variations. The charge carrier
mobility corresponds to the charge carrier velocity for a given
electric field through the semiconductor. References [6] and [7]
show respectively electrons mobility variations and holes mobility variations with respect to the temperature in intrinsic silicon
from 300 K down to 8 K. In both cases, the mobility increases
almost linearly for decreasing temperature with a slightly faster
increase for holes carrier mobility. This increase in charge carrier mobility is the results of lower atomic vibrations due to lower temperature. In our technology, the charge carrier mobility
corresponding to our doping concentration was studied in [8].
This article also shows an increase in charge carrier mobility
with decreasing temperature, but we observe a slowdown of the
26

Figure 5.

Electron density and Fermi energy trends with respect to temperature of
a 0.35 μm CMOS silicon substrate. Dots show the minimum temperature reached in our study, 77 K. Adapted from Bart Van Zeghbroeck
equations (1997).

mobility below 80 K and the mobility start to decrease below
60 K-70 K.
The second physical parameter is the charge carrier density
and depends on the doping concentration and on the energy level
to free electrons in the conduction band and holes in the valence
band. A diminution in temperature results in a diminution of the
charge carrier's density [9] due to an increase of the Fermi Level.
When the charge carrier density is too low, a drop in the transistors
current is observed; it's called the freeze-out effect [10]. Figure 5
shows the electron density and its corresponding Fermi energy for
a CMOS 0.35μm silicon substrate in function of the temperature.

IEEE A&E SYSTEMS MAGAZINE

AUGUST 2018

Aerospace and Electronic Systems - August 2018

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