IEEE Aerospace and Electronic Systems Magazine - December 2020 - 47

Furano et al.
computing parallelism of the GPUs to improve performance at the cost of higher energy consumption; and 3)
FPGA-based hardware that significantly increases the performance per watt but with limited programming capability compared to GPUs.

ASIC-BASED AI PLATFORMS
According to [27], a large number of companies have been
involved in the development of silicon AI accelerators.
These accelerators are in the form of IP cores for integration
in SoCs, single chips, or board-level platforms and integrate
an AI engine, which can compute fast vectors and matrices
operations. These accelerators target mobile devices (e.g.,
Qualcomm's Snapdragon 855, HiSilicon's Kirin 970, and
MediaTek's Helio P90), IoT edge applications (e.g., AI
AM5729 of BeagleBone) or the general use case (e.g.,
Intel's Myriad 2 and Google's Coral) [28]. In this article,
we focus on the latter case as most appropriate for use on
the edge in space systems and illustrate the Intel Myriad
platforms, as our demonstration vehicle for the radiation
experiments and the Google Coral platform as a second representative example. The reader can refer to [28]-[30] for a
more detailed description and comparison of the AI chips.

MYRIAD 2. Myriad 2 is a system-in-package (SiP) device
that contains a 28-nm SoC die fabricated in a standard
LPCMOS TSMC manufacturing process along with a
stacked 512 MB Low Power Double Data Rate (LPDDR)3
dynamic random access memory (DRAM) die [31].
The Myriad 2 architecture contains two LEON4 processors,
one for user-applications running under RTEMS real-time
operating system, and the other running a scheduler for the
image signal processing (ISP) and computer vision pipeline. In addition to the LEON4s, the device contains 12
streaming hybrid architecture vector engine (SHAVE) very
long instruction word (VLIW) digital signal processor
(DSP) processors capable of executing the equivalent of
144 RISC instructions in a single 600-MHz clock-cycle.
Finally, an ISP pipeline can process an aggregate 1 pixel
per cycle at the 600-MHz system clock rate for
600 Mpixel/s aggregate throughput. The ISP hardware contains streaming image processing pipeline (SIPP) debayering, polyphase up/down-caling filters, convolution filters,
etc. Intel's Neural Compute Stick (NCS)1 enables the
exploitation of Myriad 2 for neural network inference in a
universal serial bus (USB) form factor.
MYRIAD X. Myriad X represents the next generation of
Intel hardware accelerators for DNN inference. The
smaller the technology node (16 nm), the higher number of
SHAVE processors and the availability of a novel 512 MB
LPDDR4 memory provide Myriad X an increased efficiency and computational power with respect to a Myriad
2 solution. Furthermore, it features 4 K ISP, native 16-bit
DECEMBER 2020

floating point, and 8-bit fixed point supports. Myriad X can
reach up to 4 tera operation per second (TOPS), with a
maximum power consumption of 1.5 W. While the Myriad
2 implements the CNN pipeline largely in software on the
SHAVE processors, the Myriad X device is the first device
to bring the CNN inference hardware to market offering
aggregate 8Â more performance for CNN inference within
the same power envelope and form-factor. Intel's NCS2 is
available to exploit Myriad X for embedded applications.

GOOGLE CORAL
Google Coral is a 28-nm Tensor Product Unit (TPU) optimized for the inference of DNNs. Differently from Intel's
Myriad, Google Coral is based on systolic arrays and features around 8 MB on board memory. Google Coral demonstrated performances up to 4 TOPS, featuring a power
consumption of 2 W [29].

GPU-BASED PLATFORMS
NVIDIA Jetson is the most commonly used GPU-based
AI accelerator. It is a 20-nm Maxwell GPU, containing
128 CUDA processors. It is equipped with a Quad-core
ARM Cortex-A57 MPCore, which shares with the GPU
4 GB LPDDR4 memory. NVIDIA Jetson can provide 472
GFLoating Point OPerations (FLOPs), dissipating up to
5 W [29].

COTS FPGAs
The use of COTS FPGAs to accelerate DNNs was investigated in the literature [32]-[35]. Compared to space-qualified FPGAs, COTS FPGAs exploit more modern
technology processes, offering improved computational
power and better power consumption/performance tradeoffs and higher resource budgets at lower prices. Different
approaches are possible to deploy DNNs on board FPGAs.
For small-footprint models, fully on-chip designs, exploiting on-chip memories only, are possible [34]. The work
presented in [32] compare the FPGA approach to a solution
based on the Intel NCS1 for small-size models, demonstrating the benefits of FPGAs in terms of inference time and
energy-efficiency. For more complex DNNs, solutions
relying on external memories to store coefficients and intermediate results are generally exploited [33]. Generally, the
advantages of FPGAs compared to other COTS strictly
depend on many factors, such as the architecture, model
size, and the number of bits used for representation [30],
[32], [34], [35]. In view of this large design space, the use
of FPGAs usually requires a much longer development
time compared to Myriad 2 and other COTS devices, when
an approach based on a design from scratch is
exploited [32], [34]. Because of that, tools for automatic
model quantization and high levels synthesis were

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