IEEE - Aerospace and Electronic Systems - February 2020 - 31

enabled the system to act as a multichannel, pulsed radar
receiver. An illustration of the system's receive chain is
shown in Figure 2. In this application, incoming signals are
sampled at the radar's carrier frequency. Down conversion
takes place in the digital domain using a numerically controlled oscillator and the conversion is limited to one half of
the system's sampling rate. After down conversion, signals
are filtered and decimated, effectively limiting data rates
based on the signal's instantaneous bandwidth requirements.
A First In First Out (FIFO) buffer is used to hold processed
data until the Universal Serial Bus (USB) controller transports data to the host computer. In the sections that follow, a
description of processing stages will be discussed as well as
any custom modifications made. It should be noted that,
although firmware modifications made to this system were
specific to the limited capabilities (e.g., no DSP slices) of
the Altera Cyclone I FPGA, all firmware algorithms were
coded in Verilog and were designed for porting to larger,
more capable FPGAs with minimal effort.

SAMPLING
The USRP1 utilizes the AD9862 [10], which as a mixed signal front-end processor designed for communication applications. On-board samplers provide up to four channels of

12-b samples at rates up to 64 MSPS. Additional logic exists
to provide both real and analytic signal representations at
the device output, as well as programmable gain controls
and decimate-by-two low-pass sampling options. The frontend of the AD9862 contains a buffer for isolation and
impedance control, followed by a programmable-gain
amplifier (PGA) that can provide up to 20 dB of gain in 1
dB steps. After sampling, the device provides optional lowpass filters to provide additional out-of-band image rejection for signals less than 3=16 of the sampling rate. For users
sampling real signals at baseband, the Hilbert filter can be
used to output I/Q data samples. The Rock Springs radar
operates at a radio frequency (RF) of approximately 50
MHz, and provides a maximum instantaneous bandwidth of
approximately 1 MHz. Given these specifications, combined with the stated sampling capabilities, band-pass sampling [11] was chosen to directly sample the incoming
signal, thereby eliminating the need for an analog intermediate frequency (IF) stage and additional circuitry. With
this configuration, the AD9862 processor was configured to
sample real data, bypassing low-pass and Hilbert filters
since superior down conversion and filtering stages exist in
the receiver's on-board FPGA.

DOWN CONVERSION
Given the Rock Spring radar's RF carrier frequency
of approximately 50 MHz and its inherent bandwidth of
1 MHz, the incoming signal is band-pass filtered and

Figure 2.
Figure 1.
System overview.

FEBRUARY 2020

Block diagram illustrating the USRP receiver chain. The system
can be configured to sample 1, 2, or 4 IF channels.

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IEEE - Aerospace and Electronic Systems - February 2020

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