IEEE - Aerospace and Electronic Systems - February 2020 - 33

Seal and Urbina

Figure 5.
Custom firmware modification to FPGA providing radar pulse
synchronization and data tagging to simplify pulse alignment in
data collection software.

Figure 4.
Droop compensation filter designed to correct the five-stage CIC
filter's steep roll-off response. The resulting response remains flat
out to 0.375 of the sample rate.

produces a register width of
B ¼ N log 2 R:

(6)

The GNURadar system employs a technique known
as bit-pruning [15] to mitigate bit growth, allowing
the designer to recover valuable hardware resources.
Additional resources were reclaimed by removing the
optional decimate-by-two half-band FIR filter from the
original design. These additional resources were used to
add an additional stage to the original CIC filter, providing 8.0 dB of increased attenuation for out-of-band frequencies. To correct for droop compensation, a 31-tap
FIR filter was designed using the CIC's inverse frequency response, and placed in the GPC as an optional,
postprocessing stage. The resulting response, shown in
Figure 4, provided a flat response up to approximately
0.375 of the incoming sample rate.

DATA COLLECTION AND STORAGE
Data from the USRP1 is streamed into a GPC using a USB
2.0 connection, moving data at rates up to 32 MSPS continuously. Sustaining rates of this magnitude while maintaining system responsiveness on a nonreal-time operating
system (NRTOS) requires careful design considerations.
Given the system's primary application of meteoric
research, data integrity was the primary system requirement, while real-time reporting was of secondary importance. In the sections that follow, details of the system's
architectural design and implementation necessary to support these requirements will be provided.
FEBRUARY 2020

FPGA FIRMWARE MODIFICATIONS
The original USRP design operated in a continuous listening mode using automatic gain control to optimize SNR. In
a pulsed radar application, coherence between transmit and
receive channels is required, as well as fixed gain to assess
a target's radar cross section. Additionally, an external
gate enable signal is required to enable data collection, providing precise control over sampled range cells. Given the
pulsed operation of the system, a data tag was inserted into
the data stream to identify the first range cell of the radar
return, providing data alignment. These two modifications
required significant modification to the original USRP1
design. Figure 5 illustrates firmware modifications made to
the FPGA.The starting time of the data collection is captured precisely by synchronizing the gate enable signal
with a 1-PPS GPS signal colocated with the GPC used for
data acquisition and storage. This provides the user with
the ability to start the system remotely and synchronize
multiple systems in distributed configurations.

DATA BUFFERING
In a typical NRTOS, the system's process scheduling architecture is the primary source of data latency, with latency
variance highly dependent on the scheduling algorithm
employed (e.g., priority, fair, deadline, etc.). To alleviate
this uncertainty while preserving data integrity, a multibuffer producer/consumer (PC) [16] buffering architecture
was implemented. This architecture utilizes two threads of
execution: 1) the producer thread, and 2) the consumer
thread are used to decouple incoming data from the mechanism used for recording. The producer thread, as the name
suggests, transfers data from the receiver into a circular
buffer system, alerting the consumer thread upon completion of a buffer write. The consumer thread listens for
incoming data; processing, formatting, and storing data to

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IEEE - Aerospace and Electronic Systems - February 2020

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