IEEE - Aerospace and Electronic Systems - October 2021 - 34

Reliability Increase for Avionics Data Communication
Figure 2.
Proposed error detection method employing four verification bits.
performed in a development stage, soon enough to allow
all partakers to properly implement the method.
In general, error detection is performed by running an
algorithm on a given word. The output is a deterministic
set of bits that later can be compared against the original
word to verify if it suffered any change. The verification
function is injective, as it cannot be used to generate back
the original word. Since the verification code, or verification
bits, is shorter than the original word, it cannot be
100% effective and might suffer errors in the transmission.
The proposed method can be incorporated into any
ARINC 429 communication system as shown in Figure 2. In
this illustrated case, four verification bits are used. First, the
original word passes through the error detection algorithm,
generating the verification bits. Then, these bits are included
in the payload, replacing bits initially set as zero. The modified
word is created and can be transmitted. The receivers
must separate the verification bits from the original word,
adding zeros to these positions. Therefore, with the original
word recovered and the verification bits, the error detection
algorithm can validate the word. If it passes verification, the
word can be used; otherwise, it must be discarded.
Four types of error detection algorithms were
selected and compared to determine the best one for
ARINC 429: Four Bits cyclic redundancy code (CRC)
[23], Fletcher's checksum [24], Hamming code [25],
and five bits CRC [22]. This selection was based on
their effectiveness specifically for smaller and fixed
word size data transmission, as opposed to more
34
common larger and variable word size protocols, like
Ethernet, which can vary from 64 to 1518 bits.
The study of different checksum algorithms showed
that the One's Complement Fletcher variation, herein
called Fletcher checksum, is more efficient [24]. Fletcher
checksum, which usually uses 16 or 32 bits, was redefined
for 4 bits for ARINC 429. The 4 bits checksum is generated
by dividing the 32 bits into 16 blocks of 2 bits. Each
block has a value from zero to three. The first two blocks
are summed up and divided by three, the rest of this division
is summed up to the next block and again divided by
three. This operation is consecutively performed until all
blocks are used. At the end of this process, the last rest of
the division (four bits) will result in the Fletcher checksum.
The same operation is performed in the receiver. By
comparing the 4 bits received with the checksum calculated,
it is possible to verify whether errors occurred in the
transmission.
Hamming code [25] can be considered a sophisticated
version of the parity algorithm. It computes the weight of
every bit and executes the parity on several layers. In the
32 bits word, each bit is enumerated from 1 to 31, and the
32th is disregarded from the analysis, as it already carries
the parity. This way, it is possible to define this set of 31
items using 5 bits. Each one of the 5 bits is represented by
a parity element named P1, P2, P4, P8, and P16. Then,
odd parity is calculated for each bit in the word considering
the data transmitted. The result set P1-P16 is then
included in the word, using bits 11-15. One recent
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IEEE - Aerospace and Electronic Systems - October 2021

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