Aerospace and Electronic Systems - September 2018 - 58
Cost-Sensitive FPGA Implementation of SAR Range-Doppler Algorithm
Figure 6.
Point target before and after azimuth processing. Left: RCMC. Right: azimuth processed.
Figure 7.
Hardware configuration.
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IEEE A&E SYSTEMS MAGAZINE
SEPTEMBER 2018
Aerospace and Electronic Systems - September 2018
Table of Contents for the Digital Edition of Aerospace and Electronic Systems - September 2018