Aerospace and Electronic Systems - September 2018 - 65
Araujo, d'Amore, and Fernandes
Table 1.
Point Target Impulse Response
Pixel Position
Measured Value
(Range)
Measured Value
(Azimuth)
Max. Value as [15]
Max. Value as [17]
PSLR
Near Range
−44.11 dB
−44.01 dB
-
-
Medium Range
−44.11 dB
−39.40 dB
−20 dB
−43 dB
Far Range
−44.11 dB
−46.44 dB
-
-
Near Range
−36.36 dB
−24.64 dB
-
-
Medium Range
−36.36 dB
−23.97 dB
−17 dB
−20 dB
Far Range
−36.36 dB
−26.21 dB
-
-
ISLR - Null to Null
Table 2.
FPGA's Resource Usage
Logic Elements
Dedicated Logic
Registers
Pins
Memory kbits
Embedded
Multipliers
65,209 (57%)
35,068 (31%)
106 (20%)
814 (21%)
297 (56%)
Using two Xilinx® Virtex-6 FPGAs and also implementing the
range-Doppler algorithm, Bian et al. [11] found the value of -13.07
dB for PSLR, and -11.20 dB for ISLR.
Long Pang et al. [7] used two Xilinx® Virtex-6 FPGAs and one
Xilinx® Virtex-5 FPGA to implement the SAR processing algorithm called SPECAN (Spectrum Analysis). The measured values
for PSLR were -36.17 dB (range) and -37.12 dB (azimuth). In relation to ISLR, the values of -35.12 dB (range) and -33.47 dB (azimuth) were registered.
By comparing the PSLR quality parameter to three other implementations, it was verified that the proposed architecture presented the best performance. Considering the ISLR parameter, the
proposed architecture registered superior performance to the system implemented by Bian et al. [11] and an inferior performance to
the processor of Long Pang et al. [7].
SYNTHESIS AND PROCESSING TIME ANALYSIS
Altera® Quartus II software was used to synthesize the proposed
processor in the FPGA. The Quartus II FPGA resources usage output report can be seen in Table 2.
The test employs a 2,048 pixel × 2,048 pixel data block running
at 50 MHz. The raw data is read from an SD Card and the processed
data is sent to a LabView® application through an SPI interface.
According to the parameters of the sensor used in test (ERS-1), Nd
was calculated and a total of 584 columns had to be discarded on
each data block and transferred from one buffer to another. Hence,
1,464 columns are range processed in each data block.
The time required for computing all phases of the SAR
processing algorithm was 20.31 s. Figure 19 depicts each processing step and Table 3 lists the time demanded for each step.
The SD card reading time and the time demanded for sending
Figure 19.
Processing time.
SEPTEMBER 2018
IEEE A&E SYSTEMS MAGAZINE
65
Aerospace and Electronic Systems - September 2018
Table of Contents for the Digital Edition of Aerospace and Electronic Systems - September 2018
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