IEEE - Aerospace and Electronic Systems - September 2019 - 37

Kobayashi et al.

Figure 4.
Digital-processing module (left: top side, right: bottom side).

Figure 5.
Iris firmware architecture top-level block diagram.

data rates, this maximum SPI line rate and software processing times will limit the effective throughput. Hardware
elements are in place to allow high-rate data interfacing
via SpaceWire in the future.
The digital processing module houses an ADC to
sample the uplink signal. The total power detector and
automatic gain control (AGC) adjusts the signal level of
the sampled signal to keep the input power to the ADC
close to the optimal performance point to balance the
needs of instantaneous dynamic range and binary resolution. The receiver tracking loops are full digital
implementation, and the transmit carrier is Doppler
tracked in coherent turn-around mode using a DDS. A
pair of in-phase/quadrature (IQ) digital-to-analog converters (DAC) modulates the transmit waveform to the
downlink carrier, allowing expansion capabilities to
include any complex modulation and pulse shaping format within its bandwidth. Figure 4 shows the assembled
digital processing module.

Firmware and Signal Processing Description
The firmware architecture uses a minimal SPARC-based
LEON system that consists of an embedded fault-tolerant processor, clock and reset generator, bus controllers,
and memory controller (see Figure 5). The architecture
is centered on an advanced microcontroller bus architecture (AMBA) advanced high-speed bus (AHB), to
which the LEON core and most high-bandwidth cores
are connected. Other low-bandwidth units connect to
the AMBA advanced peripheral bus (APB), which is
accessed through an AHB-to-APB bridge. The fault-tolerant version of the LEON core includes advanced features to withstand and correct arbitrary single-event
upset errors without loss of data, critical for reliable
operation in deep-space environments. The fault-tolerance is provided at the design level and does not require
a radiation-hardened semiconductor process, nor a custom cell library or special back-end tools.
Upon power-ON of the radio, the FPGA configuration is auto-loaded, and the boot loader is executed.
The boot loader decompresses the software application,
configures various processor parameters, loads the
SEPTEMBER 2019

application into the program area of memory, and sets
the stack pointer to the start address location for application loading. The software then continues to configure
and operate the radio.
The multimission system architectural platform telecom interface module, or MTIF for short, performs the
data-handling functions for uplink and downlink. MTIF
is the standard interface controller used on command
and data handling (C&DH) subsystems for JPL missions such as the Mars Science Laboratory and Soil
Moisture Active Passive missions. It is capable of
uplink command decoding, error checking, and encoding downlink data using various forward-error correction algorithms including Reed-Solomon and Turbo
codes. On Iris, decoded uplink commands are pushed
into the uplinked buffer for collection by the C&DH
and are primarily handled outside the context of the
software for simplicity. Downlink data, on the other
hand, includes software processing to form standardized
frames prior to encoding in MTIF.
The transmit portion of the modem contains mainly
the telemetry modulator comprised of a subcarrier and
direct-carrier modulator (see Figure 6). In subcarrier
mode, the transmit carrier generator is fed with the
modulated subcarrier, the turnaround ranging tone, or
the sum of both. In direct-carrier mode, the transmit
carrier (no subcarrier) is complex multiplied with the
telemetry data. Differential one-way ranging (DOR)
tones can be modulated on top of the telemetry
modulation.
The receive portion of the modem is made up of the
total power AGC, tracking loops, and demodulator modules (see Figure 7). The carrier tracking loop acquires and
tracks the carrier frequency and phase for Doppler
compensation. After carrier and subcarrier acquisition, an
early-late gate symbol synchronizer manages the timing
of the integrate-and-dump filters to demodulate the complex IQ waveforms into symbols. Before the recovered
symbols are passed to the uplink handler, single-bit error
correction and double-bit error detection are performed on
the encoded uplink code blocks.

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