The Bridge - Issue 2, 2022 - 20

Feature
Return Path Discontinuities and Common Return Path Issues
traces, but that path is unavailable for conduction
current. The path of least impedance is around the
edge of the slit at low frequencies, as seen in Fig.
10. As the frequency increases, capacitive coupling
across the slit becomes the lower impedance path.
This change is evident in the current density plot in
Fig. 11.
The parasitic inductance for the path around the
slit and the capacitance across the slit can be
represented as a parallel LC circuit in the return path
between two transmission lines for the microstrip
on either side of the slit. More complicated models
may be used to capture the higher order resonances.
One such model would involve two slot lines. These
transmission line models would be connected in
parallel and attached across the return between
the two microstrip transmission line models. One
slot line would be terminated short and the other
open to represent the slots propagating away from
the microstrip. [6] uses a similar analysis method to
represent the slot in the reference plane.
Splitting a reference plane is seldom a perfect
situation, but there are methods to reduce the fallout
when necessary. The impact of the split plane can
be seen in the insertion loss (S_21) of the primary
microstrip in Fig. 12. Along with the partial split
shown in Fig. 9, three other variations are displayed.
Alternative high-frequency return paths can be
introduced, using SMT components attached through
low inductance paths. Each of the alternatives has an
SMT, represented by a small conducting block in the
models. The proximity of the SMT to the microstrip
heavily influences the effectiveness of this mitigation
approach. Also, if the SMT is connected to the two
sides of the reference plane by long vias, the parasitic
inductance in the connection will impede current
flow at high frequencies.
Another way of viewing the impact of the different
mitigation methods is to observe the electric field in
the slit. Fig. 13 shows the electric field across the gap
at 10 MHz. The field is similar for each variation, with
some spikes below and about the microstrip line. At
1 GHz, Fig. 14 shows a more significant difference.
Fig. 7. Far-end crosstalk of the parallel wire geometries in Fig. 6
The electric field still drops to near zero where the
SMT components are positioned, but the fields are
much higher elsewhere. These larger fields indicate
potential EMC issues. When there is a significant
voltage drop between two conductors, there is the
potential to radiate. The edge of the reference plane
can act as elements of a dipole.
Crosstalk is also an issue with the split crossing. There
is inductive coupling because the two microstrips
share part of their return path. The far-end crosstalk
between the two microstrip traces is shown in Fig. 15
and compared with the crosstalk observed for two
microstrips routed over a solid reference plane of the
same size. The crosstalk is approximately two orders
of magnitude higher than without the split crossing,
except for the frequency band between 5 GHz and
7 GHz. This band coincides with a null in the electric
field around the location of the second microstrip.
While the reader may be considering why anyone
would ever route a signal over a split in a return
plane, there are reasons where the idea is less
terrible than others. Consider that crossing a split in
a reference plane may be unavoidable. The crossing
may not be by design but due to process variation.
An unintended split crossing can be introduced
into a design by a row of large antipads. Lines of
via antipads are shown in Fig. 16, like those in
the footprint of a high-density signal connector.
The vias are necessarily close together to match
THE BRIDGE
The Bridge - Issue 2, 2022

Table of Contents for the Digital Edition of The Bridge - Issue 2, 2022
