The Bridge - Issue 2, 2022 - 23

Return Path Discontinuities and Common Return Path Issues
Feature
IV. SUMMARY AND CONCLUSIONS
The goal of this article has been to present some of
the challenges associated with controlling return path
currents and the trouble that may ensue when they
are not maintained. A key issue with many return path
discontinuities is distinguishing their impact from those
caused by discontinuities in the outgoing signal path.
TDR and other measurement techniques may not be
enough to zero in on the cause, but TDR can find the
distance of a discontinuity from the measurement
point to guide the search. How specific return path
issues manifest in example geometries was presented.
Ultimately, every situation will be subtly different, and
the best solution may not precisely align with what
was presented here. One piece of advice remains.
Follow the currents from source to load and all the
way from the load back to the source. Look for all
paths, not just the obvious ones.
REFERENCES
[1] W. Cui, X. Ye, B. Archambeault, D. White, M. Li, and J. Drewniak,
" Emi resulting from signal via transitions through the dc power bus, "
in IEEE International Symposium on Electromagnetic Compatibility.
Symposium Record (Cat. No.00CH37016), vol. 2, Aug 2000, pp.
821-826 vol.2.
[2] A. Engin, M. Coenen, H. Koehne, G. Sommer, and W. John,
" Modeling and analysis of the return path discontinuity caused by vias
using the 3-conductor model, " in 2003 IEEE International Symposium
on Electromagnetic Compatibility, 2003. EMC '03., vol. 2, May 2003,
pp. 1110-1113 Vol.2.
[3] C. Hwang, M. Ouyang, and J. Fan, " Return path discontinuity
analysis of an edge mount SMA launch structure in multilayer boards, "
IEEE Transactions on Electromagnetic Compatibility,
vol. 60, no. 2, pp. 453-458, April 2018.
[4] C. R. Paul, Analysis of Multiconductor Transmission Lines. WileyInterscience,
1994.
[5] M. Cracraft, S. Connor, and B. Archambeault, " Unintended
effects of asymmetric return vias and via array design for reduced
mode conversion, " in 2014 IEEE International Symposium on
Electromagnetic Compatibility (EMC), Aug 2014, pp. 250-255.
[6] S. A. Sis, F. U¨ stu¨ner, and E. Demirel, " Emi reducing interdigital
slot on reference planes of the PCBs, " IEEE Transactions on
Electromagnetic Compatibility, vol. 64, no. 1, pp. 219-229, 2022.
Michael Cracraft received the
B.S., M.S., and Ph.D. degrees in
electrical engineering from the
Missouri University of Science and
Technology (formerly the University
of Missouri-Rolla), Rolla, MO,
USA, in 2000, 2002, and 2007,
respectively. He received an NSF
IGERT fellowship while working
with the Electromagnetic Compatibility Laboratory, Missouri
University of Science and Technology, as a graduate student.
In 2007, he joined the IBM Systems & Technology Group in
Poughkeepsie, NY, working in packaging and signal integrity
on POWER and Z systems. Cracraft joined the Electrical &
Computer Engineering department of the Rose-Hulman
Institute of Technology in Terre Haute, IN in 2020 as an
associate professor. He specializes in high-speed and highfrequency
measurements, electromagnetic modeling, and
model-to-hardware correlation.
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