James Webb Telescope Issue - 23

Impacts of Low-Power Requirements on the LEMS HMS Design
Feature
designated as the main card and daughter card. The main
card has all the major components, such as an FPGA,
low-power oscillator (used as the FPGA clock), flash
memory, and a four-channel Analog-to-Digital Converter
(ADC). The HMS daughter card is predominantly used for
analog telemetry hardware. During the long periods of time
when the major LEMS components are asleep, the HMS
constantly monitors telemetry data from these thermistors.
To collect sufficient data, the seismometer on LEMS needs
to remain active for the mission's duration and collect data
continuously. Fortunately, the seismometer requires very
low power to operate. Thus, the seismometer can remain
powered on through the full lunation. Since the HMS
will be the only other system awake, the HMS was also
responsible for collecting and storing seismometer data
in flash memory. The seismometer data is passed to the
processor card when the processor card wakes up every
24 hours.
IV. Major HMS Board Components
The need for low power also influenced the components
chosen for the HMS boards. This begins with the FPGA,
for which the low-power Microchip ProASIC3L was
chosen. While not the most powerful or recent FPGA, the
ProASIC3L is a reliable, low-power FPGA with radiationhardened
options. A low-power 10 MHz oscillator drives
the FPGA clock.
The ADC chosen is a low-power, four-simultaneously-readchannel,
24-bit ADC. Three of the channels are used for
the seismometer, and one channel to read in multiplexed
telemetry data. The HMS utilizes four independent
analog multiplexers to read in telemetry into a single ADC
channel. Two 16-channel MUX are set up for temperature
measurements using thermistors with a current source,
and the other 16-channel MUX are for single-ended
voltage inputs.
Seismometer and telemetry data are stored periodically in
flash memory. The flash is a 64Gbit (8GB), high-density
nonvolatile CMOS NAND FLASH module. Flash acts as a
low-power method of storing seismometer and telemetry
data while the rest of LEMS is asleep. Since flash is
nonvolatile, it also provides a way to save the HMS FPGA
state information in case of a need to reset.
V. HMS FPGA Design
Jumping down to low-level hardware design, low-power
optimizations were also made when it came to low-level
FPGA design. A high-level block diagram of the HMS FPGA
design is shown in Figure 5.
It was determined early that the FPGA design would
avoid using a processor to minimize power. This is mainly
because the use of a soft-core processor is usually less
efficient in terms of area and power when compared with
a pure HDL design. To explain this, power consumption
in FPGA designs is directly correlated with transitions in
flip-flop states. A processor, by its nature, must constantly
read and execute instructions, which requires the transition
of flip-flop states. Additionally, a soft-core processor would
take up more area in the FPGA than a dedicated HDL
design, allowing for a less optimal place-and-route design.
The need for a processor-less, pure HDL design
Figure 5 - LEMS HMS FPGA Design Block Diagram
necessitated relatively simple requirements - both because
simplicity often equates to low power (for the same reasons
as noted in the paragraph above), and to allow an FPGA
developer to complete the design within a reasonable
timeframe. While a pure HDL design is often more efficient
than a processor-based design, the development time for
similar tasks can often be much longer. Thus, the HMS
FPGA design requirements were designed to be simple. For
example, complex data processing such as digital filtering of
ADC data was left as a task to be accomplished once the
data safely reached Earth.
Another early trade study for power reduction involved
the selection of the 10 MHz clock frequency. Since power
consumption is directly proportional to clock speed, it
would seem that to reduce power, one need simply to
reduce the clock speed. However, the clock speed also
determines how quickly the stored seismometer and
telemetry data can be sent out of the HMS to the processor
card over the SPI bus. The processor card must be
powered on long enough for all the data stored in the past
24 hours to be transferred. Ten MHz was selected to allow
the data to be transferred in roughly 10 minutes.
In a similar vein, the limited time for transferring data to
the processor card puts limitations on the data itself. The
amount of seismometer and telemetry data stored in flash
was capped by how long it would take to transmit all of it
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