IEEE Circuits and Systems Magazine - Q1 2018 - 33
work [5], [17] it has been suggested that negative numbers in a memristor system can be represented by using
two identical crossbars. Specifically, the weight matrix
C is split into two parts C 1 and C 2 so that C = C 1 - C 2,
where C 1 = (C) +, C 2 = (-C) +, and (x) + = max {0, x} is a
positive operator taken elementwise for a matrix argument. Given nonnegative matrices C 1 and C 2, the matrix-vector multiplication (1) can be obtained through
the subtraction C 1 VI - C 2 VI [38], [39]. Instead of using
two identical crossbars, we can eliminate the negative
numbers by introducing auxiliary variables in the linear
system (1),
(C) + B VI
VO
E ; E = ; E,
VO = CVI & ;
D I Nr Vr I
0 Nr
* C = (C) + - (-C) +, which yields VO = (C) + VI - (-C) + VI .
* Let {i 1, i 2, f, i Nr } denote the indices of nonzero
columns of (-C) + . Definitions of B = [b 1, f, b Nr ] and
D = [e i 1, f, e i N ] T in (2) give
Nr
(-C) + = / b j e Ti j = BD.
j =1
* VO = (C) + VI - BDVI ( VO = (C) + VI + BVr I with
Vr I =-DVI, which yields (2).
(2)
r
where Vr I ! R N is a newly introduced variable, Nr is the
number of nonzero columns of (-C) + (namely, the number of columns of C that contain negative elements),
r
B ! R N # N is formed by nonzero columns of (-C) +,
Nr # N
D!R
is a submatrix of I N whose row indices are given by column indices of nonzero columns of (-C ) +, and
0 Nr is a zero vector of size Nr . In Table I, we show that (1)
can be recovered from (2) by eliminating Vr I . We stress
that compared to the use of an identical memristor
crossbar (leading to 2N # 2N memristor network), the
proposed scheme (2) requires fewer memristors, resulting in the memristor network of size (N + Nr ) # (N + Nr ),
where Nr # N.
We remark that a memristor crossbar is size-limited
due to manufacturing and performance considerations
[10]. To improve its scalability, analog network-on-chip
(NoC) communication structures can be adopted to effectively coordinate multiple memristor crossbars for
supporting large-scale applications [10], [20], [48], [49].
Data transfers within the NoC structure maintain analog
form and are managed by the NoC arbiters. Two potential analog NoC structures for multiple memristor crossbars are presented in Fig. 3. Fig. 3(a) shows a hierarchical
structure of memristor crossbars [10], where four crossbar arrays are grouped and controlled by one arbiter,
and those groups again form a higher-level group controlled by a higher-level arbiter. Fig. 3(b) shows a mesh
network-based structure of memristor crossbars, which
resembles a mesh network-based NoC structure in multicore systems [49].
Furthermore, parameters of a memristor crossbar
may differ from the target values due to variability in
the fabrication process, environmental noise, and signal
fluctuations from power supplies and neighboring wires
[50]. Several methods have been proposed to mitigate
these impairments in hardware [19], [27], [28], [30], [51].
In [19], [51], feedback programming techniques were
used to improve the writing accuracy in memristor
first quarter 2018
Table 1.
Illustration of linear mapping (2).
Arbiter
2
Arbiter
1
Arbiter
1
Arbiter
Arbiter
2
(a)
Arbiter
Arbiter
Arbiter
Arbiter
(b)
Figure 3. examples of noc structures coordinating
multiple memristor crossbars. (a) four crossbar arrays are
grouped and controlled by one arbiter. the resulting higherlevel group is controlled by a higher-level arbiter. (b) mesh
network-based structure of memristor crossbars.
crossbars. In [28], a read peripheral circuitry that functions as an analog-to-digital converter was used to eliminate analog distortions. In [27], multiple memristors
were introduced to update a single weight. This method
statistically averages out the conductance variations in
ieee circuits and systems magazine
33
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