Eye-RIS VSoC Image Acquisition In-Pixel Image Memory In-Pixel Image Processing Eye-RIS v2 Vision System Nios II RISC Microprocessor Image Post-Processing, Application Control, and Decision Making Q-Eye Controller I/O Interface CVIS Q-Eye Sensor-Processor On-Chip Date and Program Memory On-Chip Image Memory DIP I/O and Communications External Image Memory Serial Flash Memory External Program and Data Memory (a) Address-Event SPA 176 × 144 NIOS-II 32 b Inst. $ 128 KB Prog. Mem 128 KB Data $ 64 KB Data Mem 64 KB 32 b 32 b Avalon Bus Ext. Mem. 12 b Prog. Mem 4 K × 32 b 32 b Register 256 × 12 b ADC 8b ADC 8b ADC 8b 8b 32 b Inst (256 × 70 b) ADC 70 b PBmem 32 b Control 12 b (b) Figure 8. Eye-rIstm vision system: (a) Block diagram; (b) architecture [19], [20], [27]. sEcOnd quartEr 2018 IEEE cIrcuIts and systEms magazInE 101