IEEE Circuits and Systems Magazine - Q2 2018 - 102

Cpij
M2

φr_ps

φacq

M5
bias

φacq

φrdm_d

φ1
φ2

Vref

φwrite_ps
φrdm

CE
M12

φwrite0

Vpix

φ2
φ1

φ1
φ2

n(i,j)

φ2
φ1

EoC

φ1
φ2
CE

M6
φwrite

Sensing

M13

M11

′
Cpij
φ2
φ1

Vdda

Pix (i,j)

φrst

n(i,j)

M10

φ2
φ1

Vdda pix

φVref_cds

φ1
φ2

φVref_ps

φrw_ps

MEM . and CDS

Vramp

φRamp_read

A /D Comp.

Gauss. Pyramid.

Figure 9. mFPs block diagram of gaussian pyramid cVIs chip [19], [26].

Figure 10. Image acquisition and different snapshots of the
on-chip gaussian pyramid. the upper left image is the input
scene, the rest of the images from left to right and top to
down correspond to v = 1, 77 (clock cyles n = 19 ), v = 2, 17
^ n = 29 h, and v = 2, 51 ^ n = 39 h [19].

case of image pyramids, such as the Gaussian pyramid [51].
Image pyramids are found at the initial stages of the processing vision chain for a large variety of computer vision
applications and algorithms such as the Scale Invariant
Feature Transform (SIFT) and variations thereof. Their
calculation is resource intensive because it involves repetitive operations with the whole set of image data. As a
consequence, calculating them with CVIS-SIMDs may represent a first step towards embedding complete computer
vision on a single die with vision capabilities into SWaP
sensitive systems such as vision-enabled wireless sensor
networks [52] or unmanned aerial vehicles [53].
102

IEEE cIrcuIts and systEms magazInE

Fig. 9 shows the block diagram of a MFPS micro-photograph of a 176 # 120 resolution CVIS designed to extract
the Gaussian pyramid [26]. This pyramid is generated
by using a switched-capacitor network embedded per
MFPS. In order to shorten routing length and speed I/O
operations up, the image is read out through two frame
buffers outside the MFPS array. Each MFPS is connected
to two 8-bit registers in the corresponding frame buffer,
allowing for reading out pixels outside the chip as they
are being A/D converted.
The scene is acquired with 4 3T-APS per MFPS with
nwell/p-subs photo-diodes. Every MFPS contains the local circuitry of an 8-bit single-slope ADC and one circuit
to perform correlated double sampling. Also, the MFPS
comprises 4 state capacitors with their corresponding
switches along the four cardinal directions to configure
a double-Euler switched-capacitor network that yields
the Gaussian pyramid.
Fig. 10 shows the image acquired by the chip and
several snapshots of the Gaussian pyramid for different values of the diffusion width, v, and the number of
clock cycles n. Deviations between images filtered onchip, on the one hand, and filtered by a conventional
computer, on the other hand are tolerated by the SIFT
algorithm [26].
This chip consumes 70 mW with scene acquisition
and the Gaussian pyramid of 3 octaves with 6 scales
each. The Gaussian pyramid is executed in 8 ms (A/D
conversions included), with 200 μs per AD conversion,
and 150 ns as the clock cycle for the switched-capacitor
network. This leads to 26.5 nJ/px at 2.64 Mpx/s. As compared to conventional architectures consisting of a CIS
sEcOnd quartEr 2018

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2018