IEEE Circuits and Systems Magazine - Q2 2018 - 91

rather disjoint groups talking different languages. the cellular
nonlinear network universal machine (cnnum) paradigm, proposed by Profs. chua and roska, defined an adequate framework for such conciliation as it is particularly well suited for
hardware-software co-design [1]-[4]. this paper overviews
cVIss chips that were conceived and prototyped at ImsE Vision
Lab over the past twenty years. some of them fit the cnnum
paradigm while others are tangential to it. all of them employ
per-pixel mixed-signal processing circuitry to achieve sensorprocessing concurrency in the quest of fast operation with reduced energy budget.

I. Introduction
picture is worth a thousand words. The scope and
meaning of this sentence are evident for human
beings. Images carry the largest percentage of
data involved in our interaction with the environment,
and we employ more than 50% of our brain processing
capabilities for handling visual scenes [5]. The same
happens for many animals, and we do not need many
arguments to get convinced of the advantages of
conferring vision capabilities to artificial sensory systems.
However, large-scale deployment of
imaging technologies was traditionally
limited by cost, Size, Weight and Power
(SWaP) constraints. Sensors employed mostly CCD technologies and delivered analog images. Camera systems built with these sensors were
costly, bulky and power hungry.
These drawbacks were particularly notorious for systems with
visual analysis capabilities, thus
rendering vision unfeasible for
many applications. This scenario
has recently changed owing to advances on CMOS pixels and CMOS
Image Sensors (CIS) architectures,
semiconductor technologies, packaging technologies, heterogeneous
integration, and system-on-chip architectures, among others [6]-[9]. All-inall, these advances have enabled imaging systems with reduced SWaP, low cost,
large speed and large functional capabilities
and flexibility. Given the relevance of the visual
sense, it is not surprising that such increased availability had resulted in imaging technologies flooding
practically all application territories. The growth rate
of inventions and revenues concerning these technolo-

gies have been impressive; the number of IP assets and
the revenue have been multiplied roughly by five in the
last decade [6], [10]. The imager market is dominated by
smartphones, notebooks, tablets and other consumer
equipment, but other sectors are rapidly growing [6].
For instance, most modern automobiles include several
cameras to continuously monitor the outside and the
inside, and many are capable of detecting pedestrians,
classifying road-signs, and other tasks.
CISs have progressed towards ever smaller pixel
pitch, and an ever larger image resolution (number of
pixels). Besides pixel scaling, other CIS challenges include [6]-[10]:
■ enhancing the image quality by improved readout, signal conditioning, and image enhancement circuitry;
■ boosting the image downloading speed by improved
communication techniques and;
■ reducing the area, power, and cost by on-chip circuit embedding.
Recent milestones include multi-million-pixel sensors with pixel-pitch around 1 μm, data rates above
10 Gpx/s [11], reconfigurable A/D conversion and readout architectures [12], [13], image correction, thermal
and energy management, etc. [9].
The last few years have also witnessed ever-increasing activities towards adding the estimation of depth,
i.e. 3-D information, to 2-D scenes. One main driver is
human-machine interfaces for the entertainment industry [14], but these technologies are also applicable
to surveillance, automotive, industrial inspection and
medicine, among other sectors with huge development
potentials. Besides techniques based on stereoscopy,
triangulation and the like, significant efforts are being
made towards modifying CMOS pixels for capturing time
information and estimate depth through Time-of-Flight
(ToF) techniques. Imaging arrays consisting of Single
Photon Avalanche Diodes (SPADs) pixels are receiving
significant interest [15]-[18]. However, ToF measurements require active illumination that complicates system implementation. Also, 3-D sensors are still lagging
behind mainstream CISs regarding the incorporation of
on-chip processing circuitry.
CVISs, the main characters of this paper, are similar
to CIS regarding physical implementation; they both include photo-sensors and CMOS processing primitives
on a common silicon substrate. Also, both CIS and CVIS
chips are similar in that they can be used as front-end
devices of complex hardware-software vision systems
[19]-[21]. Roughly speaking the front-end captures

A. Rodríguez-Vázquez, J. Fernández-Berni, J.A. Leñero-Bardallo, I. Vornicu, and R. Carmona-Galán are with the IMSE-CNM (Universidad de Sevilla-
CSIC) arodri-vazquez@us.es; angel@imse-cnm.csic.es.
sEcOnd quartEr 2018

IEEE cIrcuIts and systEms magazInE

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2018