IEEE Circuits and Systems Magazine - Q2 2018 - 95

Visual microprocessors architectures based on the CNNUM paradigm
aim at combining the best of analog and digital worlds.
devoted to image enhancement and restoration. During
this stage, non-idealities of the sensing process are compensated and the quality of captured images is improved
in relation to selected image features. This is achieved
by applying several filters (convolution masks, diffusion
process, etc.) and by performing point-to-point transformations. The output data provided by enhancement and
restoration tasks is still a matrix of real numbers, which
are the input of a second stage where feature extraction
tasks are performed. These operations typically examine
every pixel to verify if there is a feature present at that
pixel considering its neighborhood. Of interest for subsequent processing are edges, corners or interest points,
blobs or region of interest, ridges, etc. Outputs of this second stage form an irregular flow of data which are the
inputs for the high-level vision processing tasks [39], [40].
Fig. 3(b) illustrates vision-chain data evolution by
means of an application example where the target is detecting defective parts as they move on a conveyor belt.
This application is entirely executed by the EyeRISTM
system-on-chip visual microprocessor of AnaFocus Ltd.
[20]; the only data downloaded from the chip are those
codifying the classification decision. Images are acquired
in an asynchronous manner and analyzed on-line to extract several features on the basis of which the pieces
are classified as either defective or correct and a corresponding trigger signal is generated. Data reduction and
increased abstraction levels as data progress across the
chain are highlighted at the figure lettering.
Dashed oblique lines in Fig. 3(a) mark where frontend borders are located in different vision system architectures. The left-side line corresponds to systems that
employ CISs at the front-end; the right-side corresponds
to systems that employ CVISs. Operations at the left of
each borderline are performed by the corresponding system front-end while operations at the right are completed
by the remaining hardware components using as inputs
the front-end outputs. Note that CVISs enable placing the
border at a stage of the chain where data have been reduced through early processing-similar to what retinas
do [35]. Hence vision systems built with CVISs front-ends
have the potentials for larger speed and better SWaP than
those built with CISs.
Fig. 4 highlights differences between architectures
with CIS and CVIS front-ends respectively. Note that CVISs
sense and pre-process in a concurrent manner, thus sending for subsequent processing an amount of data, represented by f that is much smaller ^f % F h than the numsEcOnd quartEr 2018

ber F of raw sensor data. Indeed, in the architecture of
Fig. 4(b), processing is performed progressively by distributing processing tasks between the front-end and the
core processor sections.
Concept of CNN-Based Visual Microprocessors
There are two general classes of CVIS architectures:
■ Specific-purpose ones pick up a specific task and
implement it on silicon. This is quite common also
for other neuro-morphic systems [36], [37], [41], [42].
■ "General-purpose" mixed-signal visual microprocessors [3]. That is, processors which combine optical sensing with analog cellular spatial-temporal
dynamic circuits and some form of logic. These
processors have elementary instructions mapped
onto receptive fields [4], and embed the possibility
of storing and executing user-selectable sequences of instructions.
Visual microprocessors architectures based on the
CNNUM paradigm aim at combining the best of analog
and digital worlds. On the one hand, analog circuits are
known to excel concerning SWaP; they are smaller, faster
and require less energy than digital ones for tasks with
limited signal-to-noise-ratio requirements [43], [44]. Among
other advantages, analog techniques fully exploit the
functional capabilities offered by basic VLSI design primitives, and in particular by MOS transistors, to implement
a large variety of circuit blocks with a minimum number of
devices [3], [42]. On the other hand, digital circuits excel
regarding controllability, flexibility, and robustness.
Back in the 1960s, the building blocks for logic design
had been the various logic circuits (micro-modules) implementing different "smart" logic tasks. These had also been
used to make digital computers. The digital computer has
a key attribute due to J. Von Neumann, namely stored programmability. It means that the same core architecture, via
algorithms coded in software, can be used for a myriad of
tasks. Or, to put it in another way, the architecture is open
to the human intellect for millions of algorithmic innovations. This is the functional secret behind the success of
the digital microprocessor, first made in the early 1970s.
CNNUM-based visual microprocessors aim at mimicking
this functional secret. However, they are mixed-signal
devices which realize analog-and-logic spatial/temporal
processing tasks and hence require quite different building blocks [3]. One key aspect of visual microprocessors
is the integration of sensing and stored programmable
processing (SPP) at the analog signal array level. Among
IEEE cIrcuIts and systEms magazInE

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2018