IEEE Circuits and Systems Magazine - Q2 2018 - 99

ACE and CACE employed the CNNUM paradigm and were designed for robust
analog behaviour owing to the extensive use of dynamic biasing,
error correction and calibration loops.
within the pixel resources for analog processing, memory and programming and control of information flows
[27]. However, embedding circuitry per-pixel enlarges
the pixel pitch and may result in spatial sampling aliasing
artifacts. Despite considerations concerning the number
of pixels required for vision tasks [22], design trade-offs
arise which may require alternative architectural solutions. A sound strategy is resorting to 3-D, vertically integrated technologies for improving the pixel foot-print by
distributing the different circuit types across different
physical layers [46], [47]. This is already happening in
CIS-APSs and we are convinced that CVIS roadmap will
evolve towards 3-D architectures. Other alternatives
include using per column processors and a sub-sampled
topographic array of processors, among others.
Fig. 6 illustrates the functional structures encountered
within an industrial MFPS, namely the Q-EyeTM pixel.
This CVIS is the front-end of the Eye-RISTM vision system
from AnaFocus Ltd [20], which picture is included at the
top-right in the figure. The figure inset at the bottomright highlights the different signal modalities included
per pixel.
III. Illustrative CVIS Chips
ACE and CACE Chips
ACE (Analogic Cellular Engines) and CACE (Complex
ACEs) were devised and designed by the IMSE vision
lab over around ten years, following the proposal of improved mixed-signal circuits for analog processing and
memory [3], [44], [48], [49]. These chips employed the
CNNUM paradigm and were designed for robust analog
behaviour owing to the extensive use of dynamic biasing,
error correction and calibration loops. ACE and CACE chip
milestones are shown in the roadmap of Fig. 7, which
epitomes were the CACE2 chip [45] and the ACE16k-v2
[50] chip.
These chips demonstrated the concept of CNNUM and
the viability of ultra-fast vision front-ends with small SWaP.
Both were fabricated using standard 0.35 μm CMOS technology. The ACE16k-v2 displayed peak computing figures of 330 GOPs with 3.6 GOPs/mm2 and 82.5 GOPs/W. It
performed linear convolutions on 3 # 3 -neighborhoods in
less than 1.5 μs, image-wise Boolean combinations in less
than 200 ns, image-wise arithmetic operations in about 5 μs,
and CNN-like temporal evolutions with a time constant of
about 0.5 μs. Regarding CACE2, this chip opened vistas for
sEcOnd quartEr 2018

application of the CNNUM paradigm to the emulation of
the dynamic phenomena observed in mammalian retinas.
ACE architectures prompted the launching of the
start-up company AnaFocus Ltd. in Sevilla-Spain; they
were also transferred to the hungarian start-up AnaLogic Ltd.
Eye-RISTM Visual Processor On-Chip
Fig. 8(a) shows the block diagram of the Eye-RISTM vision
system on a chip [20]. It embeds a CVIS front-end, a Digital Image Processor (DIP), a microprocessor, memories
and I/O and communication ports. CVIS architecture follows a modified version of the CNNUM paradigm, similar
to Single Instruction Multiple Data (SIMD) processors,
consisting of an array of interconnected mixed-signal
processors, one per pixel, that operate in parallel-see
Fig. 8(b). Since the CVIS is software-controllable, the
systems must include a dedicated microprocessor to
control and configure its operation. Users can define a
particular algorithm or sequence of operations through
the NIOS microprocessor, and the microprocessor of the
CVIS controller sends the microinstructions through the
control interface.
Architecture and parameters of this CVIS are conceived
for efficient completion of pre-processing vision tasks.
The implementation of regular algorithms in hardware
involves mapping of operations onto dedicated processing elements and representation of data dependencies by
hardware interconnections or intermediate memories. For
regular algorithms of image processing, array processors
are typically derived as appropriated hardware structures. Favourable properties of array structures are the
incorporation of parallel processing and pipelining and
the locality of connections between processing elements.
Thus, high performance and throughput are obtained at
moderate hardware expense.
Parallelism and the use of mixed-signal circuitry enable
going from sensing to actuation at rates about 1 kF/s rate
with around 60 nW per pixel required. Also, software programming of the front-end features large flexibility to cope
with a wide range of machine vision applications.
Low Power CVIS for Gaussian Pyramid Extraction
Compatibility with computer vision tools is cornerstone
for CVIS adoption and can be achieved by focusing on the
embedding of pre-processing functions customarily used
by computer vision system engineers. This is actually the
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