IEEE Circuits and Systems Magazine - Q2 2019 - 35

UDA Streams

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USA Streams

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UFH Streams

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energy-efficient digital arrays. The relationship between
II. Comparative Framework
spectral efficiency (SE) and energy efficiency in par- In this work, we focus on the comparison of transmitter
tially-connected hybrid architecture is studied in [15], antenna array architectures in a 5G mmW BS. We first
[24], [25]. Works [20], [26] provided comparison among introduce three commonly considered array architecarray architectures and concluded that hybrid archi- tures and summarize recent silicon implementations.
tecture can achieve higher energy efficiency than fully Then, we describe the metrics used for comparison of
digital ones in the regime of point-to-point communica- the three architectures.
tion. Future 5G system, however, will certainly use multiuser multiplexing to provide higher network through- A. Array Architectures
put. Moreover, existing works did not study trade-offs There are three transmitter array architectures that are
among array size, transmit power, and specifications of considered for adoption in 5G mmW system. Figure 1 dekey circuit blocks in the three architectures. However, picts block diagrams of digital array and two variations of
system designers need to understand these trade-offs hybrid array, partially-connected hybrid array (we denote
and hardware implications to develop energy and cost it as sub-array in this work), and fully-connected hybrid arefficient mmW systems [27].
ray. Key design parameters for each architecture are:
■ Transmit power in all array elements: P (out)
This work aims to fulfill this gap. We intend to compare
■ Number of antennas: N
different array architectures in a comprehensive manner by
considering trade-offs among capacity, energy and area efficiency. Specifically, we compare array archiANT.
tectures based on the criterion of
DAC
1
achieving same capacity. All design
PA
LO
B
Bits
DA
trade-offs are carefully considered
in reaching most efficient design
DSP
RF-Chain 1
in all architectures which meets the
requirement of typical 5G use cases.
ANT.
Power consumption, including anaRF-Chain MDA
NDA
log processing energy and digital
(a)
computation energy, and IC area are
ANT.
then compared based on state-ofRF-Chain
1
1
the-art circuits. We provide several
PA
QSA Bits PS VGA
design insights on scaling laws and
ANT.
BSA Bits DAC
the bottlenecks in each architecture
KSA
DSP
which allow us to predict a trend for
Group 1 (KSA Elements)
future wireless demands and technology scaling.
RF-Chain
PS-Group MSA
ANT.
MSA
The paper is organized as folNSA
lows. In Section II, we briefly intro(b)
duce emerging mmW array archiANT.
tectures and typical 5G use cases.
RF-Chain
PS-Group
Σ
1
1
1
In Section III, we discuss design
PA
trade-offs in all array architectures
QFH Bits PS
BFH Bits DAC
NFH Elements
and the designs used for compariDSP
son. In Section IV, we study implementation issues in antenna arrays
ANT.
PS-Group
RF-Chain
and their impact on different archiNFH
Σ
MSA
MFH
tectures. In Section V, we present
Sum of MFH
the state-of-the-art specifications of
(c)
mmW beamforming circuits blocks
and system level power consumpFigure 1. three transmitter array architectures that are considered in this work. (a)
Block diagram of digital array, (b) Block diagram of sub-array. each rF-chain has the
tion and IC area of the three archisame structure as (a), (c) Block diagram of fully-connected hybrid array. each rF-chain
tectures. This leads us to the genand ps group has the same structure as (b).
eral conclusions in Section VI.
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