IEEE Circuits and Systems Magazine - Q2 2019 - 53

150

Power Consumption (W)

300

8

6

04

2,

1,

53

8

6

04
2,

Number of Array Elements
(b)

Number of Array Elements
(a)
350

02

1,

02

4

8

2

76

4

51

38

25

8

76

51

31

51

6

0

2

0

8

50

2
76
1, 8
02
4

50

4

100

1,

100

200

8

150

U=8
Streams

250

6

200

U=4
Streams

04

250

U=2
Streams

300

2,

U=8
Streams

53

U=4
Streams

1,

U=2
Streams

Power Consumption (W)

300

Sub-Array

350

53

Digital-Array

350

Power Consumption (W)

In Figure 9 to 11, DAC and BB precoding power has
small proportion in the DA system, even when high multiplexing or large array size is used. Part of the reason is
the ENOB requirement relaxation according to Section III.
A more important factor is the DSP energy efficiency. Our
study is based on the assumption that baseband processing is implemented on application-specific integrated circuits (ASIC). In deploying mmW DA, programmable DSP
or Field-Programmable Gate Array (FPGA) based BB processor provide flexibility of reconfiguring BB precoding
scheme, with the cost of order-of-magnitude more power
consumption [84]. In Figure 12, the system power of all

1,

the DA requires nearly 4 bits smaller quantization than
hybrid architectures according to Figure 4 and it prevents excessive power consumption in BB precoding,
SerDes and DAC. Overall in this use case, the SA and FH
have similar power consumption. In fact, SA and FH have
the same the number of phase shifters when using same
number of antenna elements. The difference between
them lies in the power consumption of signal routing.
The SA has more RF-chains than FH and therefore SA requires more power in high precision DAC and VCOs. The
FH has only one RF-chain but it requires more power for
RF signal distribution than SA.

Fully Connected Hybrid Array
U=2
Streams

U=4
Streams

U=8
Streams

250
200
150
100
50
0

BB Precoding

512 768 1,024 384 512 768
192 256 384
Number of Array Elements
(c)
SerDes

DAC

Mixer

VCO

PS

RF Amp

PA

Figure 10. total power consumption for three architectures operating in the 50+mbps everywhere use case. For each array architecture with varying array size, other design parameters are chosen according the analysis in section iii and 4.7 bps/hz se target
demands are guaranteed in the corresponding NLos environment listed in table ii.

secoND QuArter 2019

ieee circuits AND sYstems mAGAziNe

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IEEE Circuits and Systems Magazine - Q2 2019

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