IEEE Circuits and Systems Magazine - Q2 2019 - 58

[53] C. B. Peel, B. M. Hochwald, and A. L. Swindlehurst, "A vector-perturbation technique for near-capacity multiantenna multiuser communication-part I: channel inversion and regularization," IEEE Trans. Commun., vol. 53, no. 1, pp. 195-202, Jan. 2005.
[54] A. Alkhateeb, G. Leus, and R. W. Heath, "Limited feedback hybrid
precoding for multi-user millimeter wave systems," IEEE Trans. Wireless
Commun., vol. 14, no. 11, pp. 6481-6494, Nov. 2015.
[55] Y. Ghasempour, N. Prasad, M. Khojastepour, and S. Rangarajan,
"Novel combinatorial results on downlink MU-MIMO scheduling with
applications," in Proc. 13th Annu. Conf. Wireless On-demand Network Systems and Services, Feb. 2017, pp. 152-159.
[56] S. Zihir, O. D. Gurbuz, A. Kar-Roy, S. Raman, and G. M. Rebeiz, "60-GHz
64- and 256-elements wafer-scale phased-array transmitters using
full-reticle and subreticle stitching techniques," IEEE Trans. Microw.
Theory Techn., vol. 64, no. 12, pp. 4701-4719, Dec. 2016.
[57] G. Auer et al., "How much energy is needed to run a wireless network?" IEEE Wireless Commun., vol. 18, no. 5, pp. 40-49, Oct. 2011.
[58] 3GPP, NR; Overall description; Stage-2, 3rd generation partnership project (3GPP), TS 38.300, Dec. 2017. [Online]. Available: http://
www.3gpp.org/DynaReport/38300.htm
[59] F.-L. Yuan and D. Markovi, "A 13.1GOPS/mW 16-core processor for
software-defined radios in 40  nm CMOS," in Proc. Symp. VLSI Circuits
Digest Tech. Papers, June 2014, pp. 1-2.
[60] D. Cui et al., "3.2 A 320 mW 32 Gb/s 8b ADC-based PAM-4 analog
front-end with programmable gain control and analog peaking in 28 nm
CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., Jan. 2016.
[61] A. Nazemi et al., "A 36 Gb/s PAM4 transmitter using an 8b 18 Gs/s
DAC in 28 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. Digest
Tech. Papers, Feb. 2015, pp. 1-3.
[62] M. Ferriss, B. Sadhu, A. Rylyakov, H. Ainspan, and D. Friedman, "A
13.1-to-28 GHz fractional-N PLL in 32 nm SOI CMOS with a Delta-Sigma
noise-cancellation scheme," in Proc. IEEE Int. Solid-State Circuits Conf.
Digest Tech. Papers, Feb. 2015, pp. 1-3.
[63] S. Ek, T. Phlsson, A. Carlsson, A. Axholt, A. K. Stenman, and H.
Sjland, "A 16-20 GHz LO system with 115 fs jitter for 24-30 GHz 5G in
28  nm FD-SOI CMOS," in Proc. 43rd IEEE European Solid State Circuits
Conf., Sept. 2017, pp. 251-254.
[64] W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, and
M. Hossain, "A 28 GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100  fs jitter in 65  nm CMOS," in
Proc. IEEE Radio Frequency Integrated Circuits Symp., May 2016, pp.
118-121.
[65] M. Ferriss, A. Rylyakov, J. A. Tierno, H. Ainspan, and D. J. Friedman,
"A 28 GHz hybrid PLL in 32 nm SOI CMOS," IEEE J. Solid-State Circuits,
vol. 49, no. 4, pp. 1027-1035, Apr. 2014.
[66] R. Krishnan et al., "Linear massive MIMO precoders in the presence of phase noise: a large-scale analysis," IEEE Trans. Veh. Technol.,
vol. 65, no. 5, pp. 3057-3071, May 2016.
[67] R. Garg and A. S. Natarajan, "A 28-GHz low-power phased-array receiver front-end with 360° RTPS phase shift range," IEEE Trans. Microw.
Theory Techn., vol. 65, no. 11, pp. 4703-4714, Nov. 2017.
[68] G. S. Shin et al., "Low insertion loss, compact 4-bit phase shifter in
65 nm CMOS for 5G applications," IEEE Microw. Compon. Lett., vol. 26,
no. 1, pp. 37-39, Jan. 2016.
[69] F. Meng, K. Ma, K. S. Yeo, and S. Xu, "A 57-to-64-GHz 0.094-mm2 5-bit
passive phase shifter in 65-nm CMOS," IEEE Trans. VLSI Syst., vol. 24, no.
5, pp. 1917-1925, May 2016.
[70] W. Shin and G. M. Rebeiz, "60  GHz active phase shifter using an
optimized quadrature all-pass network in 45 nm CMOS," in Proc. IEEE/
MTT-S Int. Microwave Symp. Digest, June 2012, pp. 1-3.
[71] S. Shakib, M. Elkholy, J. Dunworth, V. Aparin, and K. Entesari, "A
wideband 28 GHz power amplifier supporting 8 by 100 MHz carrier aggregation for 5G in 40 nm CMOS," in Proc. IEEE Int. Solid-State Circuits
Conf., Feb. 2017, pp. 44-45.
[72] B. Moret, V. Knopik, and E. Kerherve, "A 28 GHz self-contained power amplifier for 5G applications in 28 nm FD-SOI CMOS," in Proc. IEEE 8th
Latin American Symp. Circuits Systems, Feb. 2017, pp. 1-4.
[73] S. Shakib, H. C. Park, J. Dunworth, V. Aparin, and K. Entesari, "A
highly efficient and linear power amplifier for 28-GHz 5G phased array
radios in 28-nm CMOS," IEEE J. Solid-State Circuits, vol. 51, no. 12, pp.
3020-3036, Dec. 2016.

58

ieee circuits AND sYstems mAGAziNe

[74] B. Park et al., "Highly linear mm-Wave CMOS power amplifier,"
IEEE Trans. Microw. Theory Techn., vol. 64, no. 12, pp. 4535-4544, Dec.
2016.
[75] A. Sarkar and B. A. Floyd, "A 28-GHz harmonic-tuned power amplifier in 130-nm SiGe BiCMOS," IEEE Trans. Microw. Theory Techn., vol. 65,
no. 2, pp. 522-535, Feb. 2017.
[76] A. Sarkar, F. Aryanfar, and B. A. Floyd, "A 28-GHz SiGe BiCMOS PA
with 32% efficiency and 23-dBm output power," IEEE J. Solid-State Circuits, vol. 52, no. 6, pp. 1680-1686, June 2017.
[77] K. Kim and C. Nguyen, "A 16.5-28 GHz 0.18-um BiCMOS power amplifier with flat 19.4 pm 1.2 dBm output power," IEEE Microw. Compon.
Lett., vol. 24, no. 2, pp. 108-110, Feb. 2014.
[78] D. P. Nguyen, B. L. Pham, and A. V. Pham, "A compact 29% PAE at
6 dB power back-off E-mode GaAs pHEMT MMIC doherty power amplifier at Ka-band," in Proc. IEEE MTT-S Int. Microwave Symp., June 2017,
pp. 1683-1686.
[79] Qorvo, Datasheet of TGA4544-SM, Oct. 2017. [Online]. Available:
http://www.qorvo.com/products/p/TGA4544-SM
[80] Analog-Devices, Datasheet of HMC1132, 2016. [Online]. Available:
http://www.analog.com/en/products/rf-microwave/rf-amplifiers/
power-amplifiers/hmc1132.html/product-overview
[81] K. Fujii, "Low cost Ka-band 7 W GaAs PHEMT based HPA with GaN
PHEMT equivalent performance," in Proc. IEEE Radio Frequency Integrated Circuits Symp., May 2015, pp. 207-210.
[82] S. Din, M. Wojtowicz, and M. Siddiqui, "High power and high efficiency Ka band power amplifier," in Proc. IEEE MTT-S Int. Microwave
Symp., May 2015, pp. 1-4.
[83] Y. Frans et al., "3.7 A 40-to-64 Gb/s NRZ transmitter with supplyregulated front-end in 16 nm FinFET," in Proc. IEEE Int. Solid-State Circuits Conf., Jan. 2016, pp. 68-70.
[84] F. Yuan, C. C. Wang, T. Yu, and D. Markovi, "A multi-granularity
FPGA with hierarchical interconnects for efficient and flexible mobile
computing," IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 137-149, Jan.
2015.
[85] R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc.
IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
[86] A. Pitarokoilis, E. Bjrnson, and E. G. Larsson, "Performance of the
massive MIMO uplink with OFDM and phase noise," IEEE Commun. Lett.,
vol. 20, no. 8, pp. 1595-1598, Aug. 2016.
[87] M. Abdelaziz, L. Anttila, A. Brihuega, F. Tufvesson, and M. Valkama,
"Digital predistortion for hybrid MIMO transmitters," IEEE J. Sel. Topics
Signal Process., vol. 12, no. 3, pp. 445-454, June 2018.
[88] X. Liu et al., "Beam-oriented digital predistortion for 5G massive
MIMO hybrid beamforming transmitters," IEEE Trans. Microw. Theory
Techn., vol. 66, no. 7, pp. 3419-3432, July 2018.
[89] H. Yan and D. Cabric, "Digital predistortion for hybrid precoding architecture in millimeter-wave massive MIMO systems," in Proc. IEEE Int.
Conf. Acoustics, Speech and Signal Processing, Mar. 2017, pp. 3479-3483.
[90] Y. Yu, P. G. M. Baltus, A. de Graauw, E. van der Heijden, C. S. Vaucher, and A. H. M. van Roermund, "A 60 GHz phase shifter integrated with
LNA and PA in 65  nm CMOS for phased array systems," IEEE J. SolidState Circuits, vol. 45, no. 9, pp. 1697-1709, 2010.
[91] W. B. Abbas, F. Gomez-Cuba, and M. Zorzi, "Millimeter wave receiver efficiency: a comprehensive comparison of beamforming schemes
with low resolution ADCs," IEEE Trans. Wireless Commun., vol. 16, no.
12, pp. 8131-8146, Dec. 2017.
[92] K. Roth, H. Pirzadeh, A. L. Swindlehurst, and J. A. Nossek, "A comparison of hybrid beamforming and digital beamforming with lowresolution ADCs for multiple users and imperfect CSI," IEEE J. Sel. Topics Signal Process., vol. 12, no. 3, pp. 484-498, June 2018.
[93] C. K. Wen, C. J. Wang, S. Jin, K. K. Wong, and P. Ting, "Bayes-optimal
joint channel-and-data estimation for massive MIMO with low-precision ADCs," IEEE Trans. Signal Process., vol. 64, no. 10, pp. 2541-2556,
May 2016.
[94] J. Mo, A. Alkhateeb, S. Abu-Surra, and R. W. Heath, "Hybrid architectures with few-bit ADC receivers: achievable rates and energy-rate
tradeoffs," IEEE Trans. Wireless Commun., vol. 16, no. 4, pp. 2274-2287,
Apr. 2017.
[95] H. Yan, Matlab simulation and data sheet for millimeterwave transmitter array architecture comparison, 2018. [Online]. Available: https://
github.com/yhaddint/MillimeterWaveTxArrayComparison

secoND QuArter 2019
http://www.qorvo.com/products/p/TGA4544-SM https://portal.3gpp.org/desktopmodules/Specifications/SpecificationDetails.aspx?specificationId=3191 https://portal.3gpp.org/desktopmodules/Specifications/SpecificationDetails.aspx?specificationId=3191 https://www.analog.com/media/en/sitemap_en.xml https://www.github.com/yhaddint/MillimeterWaveTxArrayComparison https://www.github.com/yhaddint/MillimeterWaveTxArrayComparison
IEEE Circuits and Systems Magazine - Q2 2019

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