30 20 10 0 −10 −20 −30 0 0.5 1 1.5 t (µs) 2 2.5 3 3 2 1 0 −1 −2 −3 Current (A) Voltage (V) A. System Design The schematic overview of the communication system is shown in Fig. 7. The system is connected directly to each of the power coils L 1+/- and L 2 +/- (compared to Fig. 3). The communication system is built identically on each side and consists of a frequency separation filter (FSF) which is connected by a transmit-receive-switch either to the transmit path or the receive path. In the transmit path an operational amplifier is used and a passive filter to protect its output. The receive path is formed by an active filter following a low noise amplifier for receive signal amplification. In Fig. 4 the circuit boards for the communication are shown. The amplifications in the transmit and receive path are optimized to maximize the SNR in the channel according to the Frequency Separation Filter The frequency separation filters, depicted in Fig. 8, realizes the frequency multiplexing between power and data channel [45]. Passive Filter In the transmit path a circuit is needed, which protects the amplifier and the microcontroller from the remaining distortions of the power signal passing the FSF. Furthermore, it needs to pass the data signal and limit the 30 30 Voltage (V), Power (W) IV. Communication Channel coupling factor k. It is defined by the IPT system and depends directly on the air gap between the coils. In systems where slight displacements or varying air gaps are possible the amplifications can be adjusted accordingly. Voltage (V), Power (W) switching process of the inverter is shown in detail. The measured signals show a good conformity to the simulations. The measurement shows a slightly more inductive behavior than the simulation. The inverter signal with a switching frequency of 500 kHz is properly provided. With 26 V input voltage an output voltage of 24.5 V is reached. The input power of 23.4 W provides an output power of 20.1 W resulting in an efficiency of h of 86.0% including the control electronics. The measured values are shown in Fig. 6(b). 20 10 0 0 0.5 1 1.5 t (µs) (a) 20 10 0 2 0 0.5 1 1.5 t (µs) (b) 2 Output Voltage Output Power Input Voltage Input Power Figure 6. In-/output voltage and power of (a) simulation and (b) measurement. L1+ L1- L2- L2+ FSF L1 L2 FSF 0 0.5 1 1.5 t (µs) 2 2.5 3 3 2 1 0 −1 −2 −3 Current (A) Voltage (V) (a) 30 20 10 0 −10 −20 −30 Figure 7. Schematic overview of the communication system. L1/2+ LW CW (b) UGS,LS1 UGS,LS2 UW iW L1/2- Figure 5. Inverter switching process of (a) simulation and (b) measurement. THIRD QUARTER 2019 LT LT RT LW Figure 8. Schematic overview of the frequency separating filter. IEEE CIRCUITS AND SYSTEMS MAGAZINE 27