IEEE Circuits and Systems Magazine - Q4 2019 - 13

in which p does not lose its state after a few operations remains an open question to us. However, this
problem can be easily remedied. That is, to save the
content of the p, whenever it is needed in the future.
Despite the overhead, this approach seems to be practically more attainable.

p
q

p IMPLY q

p IMPLY q

p = 1, q = 1

0.5
p = 1, q = 1

Relative Memristance

1

0
0

Table II.
Parameter values used in VTEAM.
Parameter voff

von

Value

0.7 V

p = 0,
q=1

kon

koff

200

300 400
Time (ns)

500

600

-10 mV 3

3

1 MΩ 10 kΩ

woff

wC

aoff

won

0 nm 107 pm 3 nm

Ron
aon
0 nm

100%
95%
85%
70%

0.2
0.1
0

700

Figure 6. Simulation of two consecutive IMPLY operations
without refreshing state of memristors (this example uses Biolek model [98]). Memristor p (blue solid line) looses its state
during the operations (black dotted line going to "1" shows
when IMPLY operation was performed), while q (green
dashed line) keeps its state as expected.

FOURTH QUARTER 2019

Roff

1
0.9
0.8
0.7
0.6
0.5
0.4
0.3

0
100

aon

aoff

-0.5 nm/s 1 cm/s 3 nm

State of Output Memristor (%)

C. Logic Example-MAGIC
Another prominent memristor-based logic is MAGIC
[39], [43]. Several logic functions can be implemented
using MAGIC, one of them being an n-input NOR, which
naturally forms a NOT gate if only one input is used. Given its attractiveness, we have tried to implement it. This
logic also faces several challenges in overcoming practical adversities of memristive circuit implementations.
Some of these challenges can be observed already
in simulations. For example, our simulations of MAGIC
NOR gates have shown that variation in memristor parameters, i.e., R on, R off, threshold current/voltage, and
switching dynamics, cause the robustness to decrease
dramatically. Simulations of these circuits were conducted using VTEAM [88]. Since VTEAM is available as a
Verilog-A model only, we implemented it in LTspice. The
implementation can be found in [106]. The used parameters for VTEAM can be found in Table II. Fig. 7 shows a
sample result of our simulations, where the effect of the
initial state on the performance can be seen, particularly
timing. For example, as it can be seen in this figure, a
5% deviation from a 100% initial state leads to a double
inversion time. Not taking this into account can lead to
incomplete state changes and eventually false results in
operations. It is appealing to think that by taking a very
long operation time this problem should go away, how-

ever, we need to bear in mind that a longer operation
time leads to a larger state drift in the input memristors.
Therefore, even though the state change in the output
memristor would be thus improved, a similar problem
would be introduced to the input memristor which would
bring us back to the same problem in further operations.
Moreover, as we showed in Section III-A, the mismatch
between memristors, which can have a similar effect as
to not fully ON or OFF initial states, could be more than
an order of magnitude larger than what is shown here.
Therefore, finding pairs or groups of memristor with similar enough properties to implement the gate is challenging too. Even harder is their inter-operation. Whereas we
successfully implemented MAGIC NOT gates (i.e., gates
involving two memristors), due to parameter variations
existing in the memristors available to us, it was barely
possible to implement 2-input NOR gates in MAGIC. It is
important to notice that our implementation of this gate
did not prove to be particularly reliable and repeatable.
We would like to remark, that this does not undermine the value and the promise of this design. The question for us (and we believe the rest of the community) is

5

10

15
20
Time (µs)

25

30

Figure 7. Dependability of the result of a MAGIC "NOT" operation on the initial state of the input memristor. The NOT
operation should yield in = 1 " out = 0 , but if the state of
in = 0.95 it already consumes twice the time to reach out = 0,
compared to the fully in = 1 state. After the original operation
time of 8 μs, the in = 0.95 yields out = 0.89 (which is a false
result).

IEEE CIRCUITS AND SYSTEMS MAGAZINE

13



IEEE Circuits and Systems Magazine - Q4 2019

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