IEEE Circuits and Systems Magazine - Q4 2019 - 16

Second is the necessity of running full functional and
corner circuit-level simulations for designed systems.
Current circuit models have room for improvement and
they do not provide a comprehensive insight as to what
may happen in the physical world. Nevertheless, they
do provide an understanding of certain potential problems in the designed systems or points where a deeper
investigation is necessary. An example of this point is
the IMPLY operation where, as presented here, most of
the existing models show that with realistic model configurations, it is most likely that consecutive operations
lead to loss of information on the p memristor. However, many system designs do not consider this potential
loss of information which can have a significant (and
potentially negative) effect on the operation of these
systems. Therefore, certain considerations (such as
refreshing the value of p in this example) are in order,
to ensure the proper operation of higher level systems
using IMPLY.
Lastly, we contend that many of the current memristive circuits, such as IMPLY for example, although having
digital inputs and outputs, operate in a manner that can
be identified better with analog CMOS circuit operations,
rather than their digital counterpart. Therefore, to reliably verify their operation, and to realistically characterize them, they need to be physically implemented and
tested. A matter that we believe is relatively overlooked
in the community and it deserves more attention. These
practical implementations show us the way forward to improve both devices and memristive circuits and systems.
Nima TaheriNejad (S'08 - M'15) re ceived his B.Sc. and M.Sc. degrees in
electrical and electronic engineering
from the Babol Nushirvani University
of Technology, Babol, Iran, and the Iran
University of Science and Technology,
Tehran, Iran, in 2007 and 2009, respectively; and the
Ph.D. degree in electrical and computer engineering
from The University of British Columbia, Vancouver,
Canada, in 2015.
He is currently a "Universitätsassistant" at the TU
Wien (formerly known also as Vienna University of
Technology), Vienna, Austria, where his areas of work
include self-awareness in resource-constrained cyberphysical systems, embedded systems, systems on chip,
memristor-based circuit and systems, health-care, and
robotics. He has published two books and more than
forty peer reviewed articles. He has also served as a
reviewer, editor, organizer, and chair for various journals, conferences, and workshops. Dr. TaheriNejad has
received several awards and scholarships from universities and conferences he has attended.
16

IEEE CIRCUITS AND SYSTEMS MAGAZINE

David Radakovits received his B.Sc. degree in electrical engineering and information technology from TU Wien, Vienna, Austria, where he is currently a
graduate student. His B.Sc. thesis was
on "Binary storage on Memristors" and
he continues to work on memristive circuits and systems for his M.Sc. degree in Embedded Systems.
His main research interests are memristive circuits
and systems, embedded systems and systems-on-chip,
and hardware security. He has two published papers and
two papers under review at IEEE journals and conferences
on different aspects of memristive circuits and systems.
References
[1] R. Iyer and E. Ozer, "Visual IoT: Architectural challenges and opportunities; toward a self-learning and energy-neutral IoT," IEEE Micro, vol.
36, no. 6, pp. 45-49, Nov. 2016.
[2] A. Carroll and G. Heiser, "An analysis of power consumption in a
smartphone," in Proc. USENIX Annu. Tech. Conf., vol. 14. Boston, MA,
2010, p. 21.
[3] D. Economou, S. Rivoire, C. Kozyrakis, and P. Ranganathan, "Fullsystem power analysis and modeling for server environments," in Proc.
IEEE Int. Symp. Computer Architecture, 2006.
[4] A. Mahesri and V. Vardhan, "Power consumption breakdown on a
modern laptop," in Proc. Int. Workshop on Power-Aware Computer Systems. Berlin, Germany: Springer-Verlag, 2004, pp. 165-180.
[5] International Technology Roadmap for Semiconductors - System Drivers, 2011th ed., ITRS Technology Working Group, 2011.
[6] S. Menzel, A. Siemon, A. Ascoli, and R. Tetzlaff, "Requirements and
challenges for modelling redox-based memristive devices," in Proc.
IEEE Int. Symp. Circuits and Systems (ISCAS), May 2018, pp. 1-5.
[7] W. Rainer, D. Regina, S. Georgi, and S. Kristof, "Redox-based resistive
switching memories nanoionic mechanisms, prospects, and challenges," Adv. Mater., vol. 21, no. 2526, pp. 2632-2663, 2009. [Online]. Available: https://onlinelibrary.wiley.com/doi/abs/10.1002/adma.200900375
[8] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The
missing memristor found," Nature, vol. 453, no. 7191, pp. 80 - 83,
2008.
[9] B. Mohammad, D. Homouz, and H. Elgabra, "Robust hybrid memristor-CMOS memory: Modeling and design," IEEE Trans. VLSI Syst., vol. 21,
no. 11, pp. 2069-2079, Nov. 2013.
[10] B. Govoreanu et al., "10×10nm2 Hf/HfOxcrossbar resistive RAM with
excellent performance, reliability and low-energy operation," in Proc.
Int. Electron Devices Meeting, Dec. 2011, pp. 31.6.1-31.6.4.
[11] A. Sinha, M. S. Kulkarni, and C. Teuscher, "Evolving nanoscale associative memories with memristors," in Proc. 11th IEEE Int. Conf. Nanotechnology, Aug. 2011, pp. 860-864.
[12] R. S. Williams, "Finding the missing memristor," 2010. Accessed
on: Nov. 6, 2017. [Online]. Available: https://www.youtube.com/
watch?v=bKGhvKyjgLY
[13] H. Kim, M. P. Sah, C. Yang, and L. O. Chua, "Memristor-based multilevel memory," in Proc. 12th Int. Workshop Cellular Nanoscale Networks
and Their Applications (CNNA), Feb. 2010, pp. 1-6.
[14] L. Chua, "Memristor - The missing circuit element," IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, 1971.
[15] D. Niu, Y. Chen, and Y. Xie, "Low-power dual-element memristor
based memory design," in Proc. ACM/IEEE Int. Symp. Low-Power Electronics and Design (ISLPED), Aug. 2010, pp. 25-30.
[16] Y. Ho, G. Huang, and P. Li, "Dynamical properties and design analysis for nonvolatile memristor memories," IEEE Trans. Circuits and Systems I, Regular Papers, vol. 58, no. 4, pp. 724-736, Apr. 2011.
[17] W. C. Shen et al., "High-K metal gate contact RRAM (CRRAM) in
pure 28nm CMOS logic process," in Proc. IEEE Int. Electron Devices Meeting (IEDM), 2012, pp. 31-36.
[18] G. Hilson, "Imec, Panasonic Push progress on ReRAM," eeTimes,
2015. [Online]. Ava ilable: https://w w w.eetimes.com/document
.asp?doc_id=1327307
FOURTH QUARTER 2019
https://onlinelibrary.wiley.com/doi/abs/10.1002/adma.200900375 https://www.youtube.com/watch?v=bKGhvKyjgLY https://www.youtube.com/watch?v=bKGhvKyjgLY https://www.eetimes.com/document.asp?doc_id=1327307 https://www.eetimes.com/document.asp?doc_id=1327307
IEEE Circuits and Systems Magazine - Q4 2019

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2019
