IEEE Circuits and Systems Magazine - Q4 2019 - 17

[19] V. Baghel and S. Akashe, "Low power memristor based 7T SRAM
using MTCMOS technique," in Proc. 5th Int. Conf. Advanced Computing
Communication Technologies (ACCT), Feb. 2015, pp. 222-226.
[20] M. Zangeneh and A. Joshi, "Design and optimization of nonvolatile
multibit 1T1R resistive RAM," IEEE Trans. VLSI Syst., vol. 22, no. 8, pp.
1815-1828, Aug. 2014.
[21] N. Taherinejad, P. D. S. Manoj, and A. Jantsch, "Memristors' potential for multi-bit storage and pattern learning," in Proc. IEEE European
Modelling Symp. (EMS), Oct. 2015, pp. 450-455.
[22] N. Taherinejad, S. M. P. D., M. Rathmair, and A. Jantsch, "Fully digital write-in scheme for multi-bit memristive storage," in Proc. 13th Int.
Conf. Electrical Engineering, Computing Science and Automatic Control
(CCE), Sept. 2016, pp. 1-6.
[23] J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for
computing," Nature Nanotechnol., vol. 8, pp. 13-24, 2013.
[24] S. Hamdioui et al., "Memristor for computing: Myth or reality?" in
Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), Mar.
2017, pp. 722-731.
[25] "Neuro-bit," Bio Inspired Technologies LLC, 2017. [Online]. Available: http://www.bioinspired.net/home.html
[26] Knowm, "Knowm Inc.," 2017. [Online]. Available: https://knowm.org
[27] P. Clarke, "TSMC to offer embedded ReR AM in 2019," eeNews,
2017. [Online]. Available: http://www.eenewsanalog.com/news/report
-tsmc-offer-embedded-reram-2019
[28] I. Vourkas and G. Sirakoulis, Memristor-Based Nanoelectronic
Computing Circuits and Architectures: Foreword by Leon Chua (Emergence, Complexity and Computation). Berlin, Germany: Springer-Verlag, 2015.
[29] S. Muroga, Threshold Logic and Its Applications. New York:
Wiley, 1971.
[30] E. Linn, R. Rosezin, C. Kügeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nature Mater.,
vol. 9, no. 5, pp. 403, 2010.
[31] E. Lehtonen and M. Laiho, "Stateful implication logic with memristors," in Proc. 2009 IEEE/ACM Int. Symp. Nanoscale Architectures. IEEE
Computer Society, 2009, pp. 33-36.
[32] J. Borghetti et al., "A hybrid nanomemristor/transistor logic circuit
capable of self-programming," Proc. Nat. Acad. Sci., vol. 106, no. 6, pp.
1699-1703, 2009.
[33] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R.
S. Williams, "Memristive switches enable stateful logic operations via
material implications," Nature, vol. 464, pp. 873-876, 2010.
[34] S. Kvatinsky, A. Kolodny, U. C. Weiser, and E. G. Friedman, "Memristor-based imply logic design procedure," in Proc. IEEE 29th Int. Conf.
Computer Design (ICCD), 2011, pp. 142-147.
[35] E. Linn, R. Rosezin, S. Tappertzhofen, R. Waser, et al. "Beyond von
Neumann logic operations in passive crossbar arrays alongside memory operations," Nanotechnology, vol. 23, no. 30, pp. 305,205, 2012.
[36] L. Gao, F. Alibart, and D. B. Strukov, "Programmable CMOS/memristor threshold logic," IEEE Trans. Nanotechnol., vol. 12, no. 2, pp. 115-119,
2013.
[37] S. Kvatinsky et al. "Memristor-based material implication (IMPLY)
logic: Design principles and methodologies," IEEE Trans. VLSI Syst., vol.
22, no. 10, pp. 2054-2066, 2014.
[38] S. Kvatinsky et al., "MAGIC-Memristor-aided logic," IEEE Trans.
Circuits Syst. II, Express Briefs, vol. 61, no. 11, pp. 895-899, Nov. 2014.
[39] G. Snider, "Computing with hysteretic resistor crossbars," Appl.
Phys. A, vol. 80, no. 6, pp. 1165-1172, 2005.
[40] A. Siemon, S. Menzel, R. Waser, and E. Linn, "A complementary resistive switch-based crossbar array adder," IEEE J. Emerg. Sel. Topics
Circuits Syst., vol. 5, no. 1, pp. 64-74, 2015.
[41] S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging
non-volatile memories," in Proc. 53nd ACM/EDAC/IEEE Design Automation Conf. (DAC), June 2016, pp. 1-6.
[42] N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, "Logic design within memristive memories using memristor-aided logic (MAGIC)," IEEE
Trans. Nanotechnol., vol. 15, no. 4, pp. 635-650, July 2016.
[43] L. Xie et al., "Scouting logic: A novel memristor-based logic design
for resistive computing," in Proc. IEEE Computer Society Annu. Symp.
VLSI (ISVLSI), July 2017, pp. 176-181.
[44] M. Teimoory, A. Amirsoleimani, J. Shamsi, A. Ahmadi, S. Alirezaee,
and M. Ahmadi, "Optimized implementation of memristor-based full adFOURTH QUARTER 2019

der by material implication logic," in Proc. 21st IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), 2014, pp. 562-565.
[45] X. Wang et al., "Memristor-based XOR gate for full adder," in Proc.
35th Chinese Control Conf. (CCC), 2016, pp. 5847-5851.
[46] M. Hu et al., "Dot-product engine for neuromorphic computing:
programming 1T1M crossbar to accelerate matrix-vector multiplication," in Proc. 53rd Annu. Design Automation Conf. ACM, 2016, p. 19.
[47] S. G. Rohani and N. TaheriNejad, "An improved algorithm for imply
logic based memristive full-adder," in Proc. IEEE 30th Canadian Conf.
Electrical and Computer Engineering (CCECE), Apr. 2017, pp. 1-4.
[48] N. TaheriNejad, T. Delaroche, D. Radakovits, and S. Mirabbasi, "A semiserial topology for compact and fast IMPLY-based memristive full adders,"
in Proc. IEEE New Circuits and Systems Symp. (NewCAS), 2019, pp. 1-5.
[49] P. Mazumder, S.-M. Kang, and R. Waser, "Memristors: Devices, models, and applications," Proc. IEEE, vol. 100, no. 6, pp. 1911-1919, 2012.
[50] Y. Pershin and M. Di Ventra, "Neuromorphic, digital, and quantum
computation with memory circuit elements," Proc. IEEE, vol. 100, no. 6,
pp. 2071-2080, June 2012.
[51] Y. V. Pershin, S. L. Fontaine, and M. D. Ventra, "Memristive model of
amoeba learning," Phys. Rev. E, vol. 80, pp. 1-6, 2009.
[52] A. Thomas, "Memristor-based neural networks," J. Phys. D, Appl.
Phys., vol. 46, no. 9, p. 093,001, 2013.
[53] M. D. Pickett, G. Medeiros-Ribeiro, and R. S. Williams, "A scalable
neuristor built with Mott memristors," Nature Mater., vol. 12, no. 2, p.
114, 2013.
[54] V. Milo et al., "Demonstration of hybrid CMOS/RRAM neural networks with spike time/rate-dependent plasticity," in Proc. IEEE Int. Electron Devices Meeting (IEDM). IEEE, 2016, pp. 16-18.
[55] A. Zaher, P. Hfliger, F. Puppo, G. D. Micheli, and S. Carrara, "Novel
readout circuit for memristive biosensors in cancer detection," in IEEE
Biomedical Circuits and Systems Conf. (BioCAS) Proc., Oct. 2014, pp.
448-451.
[56] M. A. Zidan, J. P. Strachan, and W. D. Lu, "The future of electronics based on memristive systems," Nature Electron., vol. 1, pp. 22-29,
2018.
[57] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu,
"Nanoscale memristor device as synapse in neuromorphic systems,"
Nano Lett., vol. 10, no. 4, pp. 1297-1301, 2010.
[58] K.-H. Kim et al., "A functional hybrid memristor crossbar-array/
CMOS system for data storage and neuromorphic applications," Nano
Lett., vol. 12, no. 1, pp. 389-395, Jan. 2012.
[59] F. Alibart, E. Zamanidoost, and D. B. Strukov, "Pattern classification by memristive crossbar circuits using ex situ and in situ training,"
Nature Commun., vol. 4, 2013.
[60] R. Fackenthal et al., "19.7 A 16Gb ReRAM with 200MB/s write and
1GB/s read in 27nm technology," in Proc. IEEE Int. Solid-State Circuits
Conf. Dig. Technical Papers (ISSCC), 2014, pp. 338-339.
[61] M. Prezioso, F. Merrikh-Bayat, B. Hoskins, G. Adam, K. K. Likharev,
and D. B. Strukov, "Training and operation of an integrated neuromorphic network based on metal-oxide memristors," Nature, vol. 521, no.
7550, p. 61, 2015.
[62] P. M. Sheridan, F. Cai, C. Du, W. Ma, Z. Zhang, and W. D. Lu, "Sparse
coding with memristor networks," Nature Nanotechnol., vol. 12, no. 8,
p. 784, 2017.
[63] Q. Chen, X. Wang, H. Wan, and R. Yang, "A logic circuit design for
perfecting memristor-based material implication," IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 36, no. 2, pp. 279-284, 2017.
[64] R. B. Hur and S. Kvatinsky, "Memory processing unit for in-memory processing," in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures
(NANOARCH), July 2016, pp. 171-172.
[65] R. B. Hur and S. Kvatinsky, "Memristive memory processing unit
(MPU) controller for in-memory processing," in Proc. IEEE Int. Conf. Science Electrical Engineering (ICSEE), Nov. 2016, pp. 1-5.
[66] P.-E. Gaillardon et al., "The programmable logic-in-memory (PLiM)
computer," in Proc. IEEE Design, Automation & Test in Europe Conf. &
Exhibition (DATE), 2016, pp. 427-432.
[67] G. Papandroulidakis, I. Vourkas, A. Abusleme, G. C. Sirakoulis, and
A. Rubio, "Crossbar-based memristive logic-in-memory architecture,"
IEEE Trans. Nanotechnol., vol. 16, no. 3, pp. 491-501, May 2017.
[68] R. B. Hur, N. Wald, N. Talati, and S. Kvatinsky, "SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided
logic," in Proc. 36th Int. Conf. Computer-Aided Design. Piscataway, NJ:
IEEE Press, 2017, pp. 225-232.
IEEE CIRCUITS AND SYSTEMS MAGAZINE

17
http://www.bioinspired.net/home.html https://www.knowm.org http://www.eenewsanalog.com/news/report-tsmc-offer-embedded-reram-2019 http://www.eenewsanalog.com/news/report-tsmc-offer-embedded-reram-2019
IEEE Circuits and Systems Magazine - Q4 2019

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2019
