IEEE Circuits and Systems Magazine - Q1 2020 - 15

DC supply voltage. Moreover, each TIA is simulated
while targeting four different cases, those cases can be
summarized as follows:
1) 10 pF PD capacitance and 5 KHz BW while targeting minimum input referred noise.
2) 10 pF PD capacitance and 5 KHz BW while targeting minimum power consumption.
3) 2 pF PD capacitance and 100 MHz BW while targeting minimum input referred noise.
4) 2 pF PD capacitance and 100 MHz BW while targeting minimum power consumption.
Since the detected optical signal is very weak, a large
area integrated PD has to be used to collect most of the
reflected optical power. It can be interpolated from [39]
that a 0.12 mm 2 PD will have a junction capacitance of
approximately 10 pF. Thus, 10 pF PD input capacitance is
chosen for 5 KHz BW cases.
On one hand, a 5 KHz BW is chosen because the majority of biomedical application in the literatures seek a similar BW value for PPG based sensors [39] and continuous
wave NIRS receivers [40]. Despite that the actual frequency contents of the PPG signal lies between 0.5 Hz and 5 Hz
[4], the duty cycle control of the transmitting LED, which
serves to control the emitted power, is done at multiple
KHz speed [41]. Thus, a TIA that has much higher BW
than the frequency contents of the PPG is essential. However, attaining such a low BW (0.5 Hz to 5 Hz) in the succeeding stages is also necessary to reject the out of band
noise and to achieve the required sensitivity. Some techniques are widely adopted to attain this low BW without
sacrificing the chip area like MOS-Pseudo resistor [42],
Miller capacitance multiplication [43], and a Block [44].
Those techniques are beyond the scope of this work.
On the other hand, the 100 MHz BW is chosen to assist the designers of higher BW biomedical applications
like frequency domain NIRS (FD-NIRS) which utilizes
100 MHz BW or more with a relatively smaller PD capacitance [45]. A 1.5 pF PD is used in the FD-NIRS optical
receiver presented in [46]. Thus, a 2 pF PD is considered
reasonable for this application.
This paper is organized as follows, the transimpedance gain and noise mathematical models of each TIA
topology are presented and discussed in the second
section. The third section introduces the simulation results for the four mentioned cases with comparisons and
discussions. The last section concludes the results and
provides suggestions to the designer on what topology
to use according to the target and device requirements.
II. TIAs Topologies
In this section, the transimpedance gain and the input referred noise current spectral density mathematical models are presented and discussed for all of the previously
FIRST QUARTER 2020

mentioned TIAs topologies. The values of the resistances
and MOSFETs' widths are tabulated for each simulation
case at the end of each circuit subsection. Channel lengths
of all MOSFETS are set to the minimum 120 nm length.
A. Common Source TIA (CS-TIA)
The CS-TIA is shown in Fig. 4. It uses a conventional CS
voltage amplifier as the core amplifier with the shuntshunt feedback to realize the current to voltage amplification. The topology is widely used since it is simple to
design and occupies small chip area [47]-[49]. The transimpedance gain formula of the CS-TIA is described by:
Z (S )TIA =

R out - ; A CS ; R F
H (S 2 ) + H (S ) + ; A CS ; + 1

(1a)

Z (0) TIA - - R F

(1b)

H (S 2 ) = S 2 C in C out R F R out

(1c)

H (S ) = S [(R F + R out) C PD + R out C out]

(1d)

where R out and A CS are the open loop output resistance
and the open loop gain of the CS amplifier respectively
described by:
R out = R D // ron

(2)

A CS = - g mn R out

(3)

Using the feedback theory, the zero frequency input
impedance is described by:
Z (0) in = R out + R F
; A CS ; + 1

(4)

The total input capacitance including the miller effect
is described by:
C in = C PD + ( ; A CS ; + 1)C gdn

(5)

VDD

RD
RF
Vout
Mn
IPD

Cout

CPD

Figure 4. Schematic diagram of the CS-TIA.

IEEE CIRCUITS AND SYSTEMS MAGAZINE

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IEEE Circuits and Systems Magazine - Q1 2020

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