IEEE Circuits and Systems Magazine - Q1 2020 - 16

where C PD is the PD junction capacitance, C gdn is the
gate to drain capacitance of the NMOS transistor. Assuming that C in is very large compared to C out and it
forms the dominant pole of the response, the BW can be
approximated by:
BW -

; A CS ; + 1
1
=
2rZ (0) in C in 2r (R out + R F ) C in

(6)

It is clear from equations (4) and (6) that due to the
feedback topology nature, the input impedance can be
decreased with increasing the open loop gain which
enhances the BW. However, increasing the open loop
gain will result in a higher DC current consumption.
Moreover, further increase in the open loop gain will increase the miller effect which at the end limits the BW
enhancement. Therefore, a trade-off is manifested between the BW and the power consumption.
The total input referred noise current of the CS-TIA
is described by:
I n2, in = 4K B T =

g 2mn + (2rf C PD)2
RF
(1 - g mn R F )2
1 + (2rf C PD R F ) 2 1
+
+ g mn c mG
c
RD
(1 - g mn R F ) 2

(7)

Table I.
Simulation parameters of the CS-TIA.
Case

WMn

RD

RF

5 KHz, Minimum Noise

8 μm

3 KΩ

11.5 MΩ

5 KHz, Minimum Power

1.56 μm

9 KΩ

10 MΩ

100 MHz, Minimum Noise

25 μm

1.5 KΩ

4.8 KΩ

100 MHz, Minimum Power

18 μm

9 KΩ

2.7 KΩ

VDD

Cgdp

Mp

where K B is the Boltzmann constant, T is the temperature in Kelvin, and c is the MOSFET noise factor. The first
term of equation (7) is the input noise contribution of R F ,
the second term is the input noise due to M n and R D .
In addition, equation (7) reveals that the noise contribution of R F dominates at low frequencies and the noise of
M n dominates at high frequencies. It is clear from equation (7) that there is a severe trade-off between the noise
and g mn, and so the power consumption. For example, as
g mn is reduced by shrinking the width of the transistor, the
DC biasing current will decrease, however, the noise will be
increased as well and vice versa. Moreover, it can be observed that at high frequencies, the noise of R F is inversely
proportional to its value which results in a lower total input
noise at higher transimpedance gain. However, increasing
R F will also shrink the TIA's BW, see equation (6).
Furthermore, increasing R D reduces the total input
noise according to the second term of equation (7) and
also enhances the open loop gain. However, the value of
R D cannot be increased beyond a certain limit to maintain
a suitable voltage headroom and ensure NMOS saturation.
The value of transistor sizing and resistances values for
the four mentioned simulation cases are listed in table I.
B. Inverter TIA (Inv-TIA)
The schematic diagram of the Inv-TIA is shown in Fig. 5. It
uses a CMOS inverter as a core amplifier (M n, M p) with a
shunt-shunt feedback resistor (R F ) to realize the current
to voltage amplification. CMOS inverter has been widely
used as the core amplifier in many proposed high performance designs [50]-[54]. The Inv-TIA can provide a higher open loop gain and a higher gain bandwidth product
(GBW) compared to the CS-TIA. This is due to the higher
obtainable effective transconductance which is the sum
of both NMOS and PMOS transconductances. Moreover,
higher drain to source resistance provided by the active
load M p at the same DC voltage drop is achieved compared to the passive resistor in the CS-TIA. The transimpedance gain of the Inv-TIA is described by:
Z (S ) TIA =

RF

R out - ; A Inv ; R F
H (S 2 ) + H (S ) + ; A Inv ; + 1

Z (0) TIA - - R F

Cgdn

(8b)

H (S 2 ) = S 2 C in C out R F R out

(8c)

H (S ) = S [(R F + R out)C in + R out C out]
Mn
IPD

CPD

Figure 5. Schematic diagram of the Inv-TIA.
16

IEEE CIRCUITS AND SYSTEMS MAGAZINE

(8a)

(8d)

Cout

where A Inv and R out are the open loop gain and the
open loop output resistance respectively which are described by:
A Inv = -G m R out = -( g mn + g mp) R out
R out = rop // ron

(9)
(10)

FIRST QUARTER 2020
IEEE Circuits and Systems Magazine - Q1 2020

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2020
