IEEE Circuits and Systems Magazine - Q1 2020 - 17

where ron and rop are the drain-source resistances of M n
and M p respectively, C in is the total input capacitance
consisted of the PD junction capacitance and the miller
capacitance due to C gdn and C gdp described by:
C in = C PD + (C gdn + C gdp) ( ; A Inv ; + 1)

(11)

Using the feedback theory, the zero frequency input
impedance is described by:
Z (0) in = R out + R F
; A Inv ; + 1

(12)

miller capacitance introduced in the input is greatly reduced compared to both the CS-TIA and the Inv-TIA [29].
This is because the drains of the transistors M n1 and
M p1 are connected to the source of the cascode transistors M n2 and M p2 . Thus, the resistances that are seen
from the drains of M n1 and M p1 are almost equal to g -mn1 2
and g -mp1 2 respectively which are very small. Accordingly, the poles introduced due to the miller effect are
shifted toward a higher frequency resulting in a greater
BW compared to the CS-TIA and the Inv-TIA at the same
transimpedance gain. The transimpedance gain of the
InvCas-TIA is described by:

Assuming that C in is very large compared to C out so
that the input pole is the dominant pole, the BW can
then be approximated by:
BW -

; A Inv ; + 1
1
=
2rZ (0) in C in 2r (R out + R F ) C in

I n2, in = 4K B T =

(15a)
(15b)

H (S 2 ) = S 2 C PD C out R F R out

(15c)

H (S ) = S [(R F + R out) C PD + R out C out]

(15d)

Table II.
Simulation parameters of the Inv-TIA.
Case

WMn

WMp

RF

5 KHz, Minimum Noise

6 μm

7 μm

14.2 MΩ

5 KHz, Minimum Power

0.55 μm

1 μm

14.2 MΩ

100 MHz, Minimum Noise

18 μm

12 μm

9.5 KΩ

100 MHz, Minimum Power

3 μm

4 μm

4.6 KΩ

2

G + (2rfC PD)
RF
(1 - G m R F )2
1 + (2rf C PD R F )2
+
(g mn c n + g mp c p)G
(1 - G m R F )2

(14)

VDD

where the first term is the noise of R F and the second
term is the noise contribution of M n and M p . Equation (14) reveals that R F noise term dominates at low
frequencies while the core amplifier's noise term dominates at higher frequencies. It should be denoted that
the noise performance of the Inv-TIA is greater than that
of the CS-TIA due to the increase of the transconductance G m at the same DC biasing current. Similar to the
CS-TIA, a trade-off between the DC biasing (power consumption) and the input referred noise is observed. The
value of transistors widths and resistances values used
in the simulation are listed in table II.
C. Inverter Cascode based TIA (InvCas-TIA)
The InvCas-TIA is shown in Fig. 6. It is an enhanced version of the Inv-TIA with a two introduced cascode transistors (M n2, M p2) which increase the open loop gain
and enhance the GBW of the TIA. Also, the effect of the
FIRST QUARTER 2020

R out - ; A InvCas ; R F
H (S 2 ) + H (S ) + ; A InvCas ; + 1

Z (0) TIA - - R F

(13)

It is clear from equation (9) that the open loop gain
of the Inv-TIA is higher than the open loop gain of the
CS-TIA due to:
1) The higher effective transconductance (G m).
2) The higher open loop output resistance that can
be achieved at the same output DC voltage due to
the active load M p .
Accordingly, the Inv-TIA can achieve the same GBW
at a lower power consumption compared to the CS-TIA.
The input referred noise current of the Inv-TIA is described by:
2
m

Z (S ) TIA =

Mp1
Mp2

VDD

RF

Mn2
VB
Mn1
IPD

Cout

CPD

Figure 6. Schematic diagram of the InvCas-TIA.

IEEE CIRCUITS AND SYSTEMS MAGAZINE

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IEEE Circuits and Systems Magazine - Q1 2020

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